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Rev | Author | Line No. | Line |
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1186 | savelij | 1 | ifndef __stm8stim3inc ; avoid multiple inclusion |
2 | __stm8stim3inc equ 1 |
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3 | |||
4 | save |
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5 | listing off ; no listing over this file |
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6 | |||
7 | ;**************************************************************************** |
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8 | ;* * |
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9 | ;* AS 1.42 - File TIM3.INC * |
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10 | ;* * |
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11 | ;* contains SFR and Bit Definitions for STM8S Timer 3 * |
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12 | ;* * |
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13 | ;**************************************************************************** |
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14 | |||
15 | __deftim3 macro Base,DIER |
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16 | TIM3_CR1 label Base+$00 ; TIM3 control register 1 |
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17 | TIM3_ARPE bit TIM3_CR1,7 ; Auto-reload preload enable |
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18 | TIM3_OPM bit TIM3_CR1,3 ; One-pulse mode |
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19 | TIM3_URS bit TIM3_CR1,2 ; Update request source |
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20 | TIM3_UDIS bit TIM3_CR1,1 ; Update disable |
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21 | TIM3_CEN bit TIM3_CR1,0 ; Counter enable |
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22 | TIM3_IER label Base+DIER+$01 ; TIM3 interrupt enable register |
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23 | TIM3_CC3IE bit TIM3_IER,3 ; Capture/compare 3 interrupt enable |
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24 | TIM3_CC2IE bit TIM3_IER,2 ; Capture/compare 2 interrupt enable |
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25 | TIM3_CC1IE bit TIM3_IER,1 ; Capture/compare 1 interrupt enable |
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26 | TIM3_UIE bit TIM3_IER,0 ; Update interrupt enable |
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27 | TIM3_SR1 label Base+DIER+$02 ; TIM3 status register 1 |
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28 | TIM3_CC3IF bit TIM3_SR1,3 ; Capture/compare 3 interrupt flag |
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29 | TIM3_CC2IF bit TIM3_SR1,2 ; Capture/compare 2 interrupt flag |
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30 | TIM3_CC1IF bit TIM3_SR1,1 ; Capture/compare 1 interrupt flag |
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31 | TIM3_UIF bit TIM3_SR1,0 ; Update interrupt flag |
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32 | TIM3_SR2 label Base+DIER+$03 ; TIM3 status register 2 |
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33 | TIM3_CC3OF bit TIM3_SR2,3 ; Capture/compare 3 overcapture flag |
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34 | TIM3_CC2OF bit TIM3_SR2,2 ; Capture/compare 2 overcapture flag |
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35 | TIM3_CC1OF bit TIM3_SR2,1 ; Capture/compare 1 overcapture flag |
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36 | TIM3_EGR label Base+DIER+$04 ; TIM3 event generation register |
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37 | TIM3_CC3G bit TIM3_EGR,3 ; Capture/compare 3 generation |
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38 | TIM3_CC2G bit TIM3_EGR,2 ; Capture/compare 2 generation |
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39 | TIM3_CC1G bit TIM3_EGR,1 ; Capture/compare 1 generation |
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40 | TIM3_UG bit TIM3_EGR,0 ; Update generation |
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41 | TIM3_CCMR1 label Base+DIER+$05 ; TIM3 capture/compare mode register 1 |
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42 | TIM3_OC1M bfield TIM3_CCMR1,4,3 ; Output compare 1 mode |
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43 | TIM3_OC1PE bit TIM3_CCMR1,3 ; Output compare 1 preload enable |
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44 | TIM3_CC1S bfield TIM3_CCMR1,0,2 ; Capture/compare 1 selection |
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45 | TIM3_IC1F bfield TIM3_CCMR1,4,4 ; Input capture 1 filter |
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46 | TIM3_IC1PSC bfield TIM3_CCMR1,2,2 ; Input capture 1 prescaler |
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47 | TIM3_CCMR2 label Base+DIER+$06 ; TIM3 capture/compare mode register 2 |
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48 | TIM3_OC2M bfield TIM3_CCMR2,4,3 ; Output compare 2 mode |
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49 | TIM3_OC2PE bit TIM3_CCMR2,3 ; Output compare 2 preload enable |
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50 | TIM3_CC2S bfield TIM3_CCMR2,0,2 ; Capture/compare 2 selection |
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51 | TIM3_IC2F bfield TIM3_CCMR2,4,4 ; Input capture 2 filter |
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52 | TIM3_IC2PSC bfield TIM3_CCMR2,2,2 ; Input capture 2 prescaler |
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53 | TIM3_CCER1 label Base+DIER+$07 ; TIM3 capture/compare enable register 1 |
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54 | TIM3_CC2P bit TIM3_CCER1,5 ; Capture/compare 2 output polarity |
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55 | TIM3_CC2E bit TIM3_CCER1,4 ; Capture/compare 2 output enable |
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56 | TIM3_CC1P bit TIM3_CCER1,1 ; Capture/compare 1 output polarity |
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57 | TIM3_CC1E bit TIM3_CCER1,0 ; Capture/Compare 1 output Enable |
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58 | TIM3_CNTRH label Base+DIER+$08 ; TIM3 counter high |
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59 | TIM3_CNTRL label Base+DIER+$09 ; TIM3 counter low |
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60 | TIM3_PSCR label Base+DIER+$0a ; TIM3 prescaler register |
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61 | TIM3_ARRH label Base+DIER+$0b ; TIM3 auto-reload register high |
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62 | TIM3_ARRL label Base+DIER+$0c ; TIM3 auto-reload register low |
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63 | TIM3_CCR1H label Base+DIER+$0d ; TIM3 capture/compare register 1 high |
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64 | TIM3_CCR1L label Base+DIER+$0e ; TIM3 capture/compare register 1 low |
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65 | TIM3_CCR2H label Base+DIER+$0f ; TIM3 capture/compare reg. 2 high |
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66 | TIM3_CCR2L label Base+DIER+$10 ; TIM3 capture/compare register 2 low |
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67 | endm |
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68 | |||
69 | restore |
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70 | endif ; __stm8stim3inc |