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1186 savelij 1 
		ifndef	__regf0822inc
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__regf0822inc	equ	1
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                save
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		listing off		; no listing over this file
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;****************************************************************************
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;*                                                                          *
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;*   AS 1.42 - File F0822.INC                                               *
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;*                                                                          *
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;*   Contains Bit & Register Definitions for Z8encore F0822                 *
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;*   Source: Z8 Encore! XP F0822 Series Product Specification, PS022518-1011*
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;*                                                                          *
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;****************************************************************************
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		include	"ez8com.inc"
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17 
;----------------------------------------------------------------------------
18 
; System Control
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20 
 
21 
;----------------------------------------------------------------------------
22 
; Flash Options
23 
 
24 
OPTIONS0	label	0000h
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WDT_RES		__z8cbit OPTIONS0,7	;  Watchdog Timer Reset
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WDT_AO		__z8cbit OPTIONS0,6	;  Watchdog Timer Always On
27 
OSC_SEL		__z8cbfield OPTIONS0,4,2 ;  Oscillator Mode Selection
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VBO_AO		__z8cbit OPTIONS0,3	;  Voltage Brown-Out Protection Always On
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FRP		__z8cbit OPTIONS0,2	;  (Flash) Read Protect
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FWP		__z8cbit OPTIONS0,0	;  Flash Write Protect
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OPTIONS1	label	0001h
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33 
;----------------------------------------------------------------------------
34 
; Interrupts Vectors
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36 
RESET_vect	label	0002h		; Reset (not an interrupt)
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WDT_vect	label	0004h		; Watchdog Timer
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ILL_INST_vect	label	0006h		; Illegal Instruction Trap (not an interrupt)
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TIMER1_vect	label	000ah		; Timer 1
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TIMER0_vect	label	000ch		; Timer 0
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UART_RX_vect	label	000eh		; UART Receiver
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UART_TX_vect	label	0010h		; UART Transmitter
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I2C_vect	label	0012h		; I2C
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SPI_vect	label	0014h		; SPI
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		if	__hasadc
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ADC_vect	label	0016h		; ADC
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		endif
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A7_vect		label	0018h		; Port A7, selectable rising or falling input edge
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A6_vect		label	001ah		; Port A6, selectable rising or falling input edge or Comparator Output
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A5_vect		label	001ch		; Port A5, selectable rising or falling input edge
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A4_vect		label	001eh		; Port A4, selectable rising or falling input edge
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A3_vect		label	0020h		; Port A3 or Port D3, selectable rising or falling input edge
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A2_vect		label	0022h		; Port A2 or Port D2, selectable rising or falling input edge
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A1_vect		label	0024h		; Port A1, selectable rising or falling input edge
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A0_vect		label	0026h		; Port A0, selectable rising or falling input edge
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C3_vect		label	0030h		; Port C3, both input edges
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C2_vect		label	0032h		; Port C2, both input edges
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C1_vect		label	0034h		; Port C1, both input edges
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C0_vect		label	0036h		; Port C0, both input edges
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61 
;----------------------------------------------------------------------------
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; Interrupts
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64 
__defirq	macro	NUM,Base
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IRQ{NUM}	sfr	Base+0		; Interrupt Request n
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IRQ{NUM}ENH	sfr	Base+1		; IRQn Enable High Bit
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IRQ{NUM}ENL	sfr	Base+2		; IRQn Enable Low Bit
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		endm
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		__defirq "0",0fc0h
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		__defirq "1",0fc3h
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		__defirq "2",0fc6h
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74 
T1I		__z8bit IRQ0,6		;  Timer 1 Interrupt Request
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T0I		__z8bit IRQ0,5		;  Timer 0 Interrupt Request
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U0RXI		__z8bit	IRQ0,4		;  UART 0 Receiver Interrupt Request
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U0TXI		__z8bit	IRQ0,3		;  UART 0 Transmitter Interrupt Request
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I2CI		__z8bit	IRQ0,2		;  I2C Interrupt Request
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SPII		__z8bit	IRQ0,1		;  SPI Interrupt Request
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		if	__hasadc
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ADCI		__z8bit IRQ0,0		;  ADC Interrupt Request
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		endif
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84 
T1ENH		__z8bit	IRQ0ENH,6	;  Timer 1 Interrupt Enable & Priority
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T1ENL		__z8bit	IRQ0ENL,6
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T0ENH		__z8bit	IRQ0ENH,5	;  Timer 0 Interrupt Enable & Priority
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T0ENL		__z8bit	IRQ0ENL,5
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U0RENH		__z8bit	IRQ0ENH,4	;  UART 0 Receive Interrupt Enable & Priority
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U0RENL		__z8bit	IRQ0ENL,4
90 
U0TENH		__z8bit	IRQ0ENH,3	;  UART 0 Transmit Interrupt Enable & Priority
91 
U0TENL		__z8bit	IRQ0ENL,3
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I2CENH		__z8bit	IRQ0ENH,2	;  I2C Interrupt Enable & Priority
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I2CENL		__z8bit	IRQ0ENL,2
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SPIENH		__z8bit	IRQ0ENH,1	;  SPI Interrupt Enable & Priority
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SPIENL		__z8bit	IRQ0ENL,1
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		if	__hasadc
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ADCENH		__z8bit	IRQ0ENH,0	;  ADC Interrupt Enable & Priority
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ADCENL		__z8bit	IRQ0ENL,0
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		endif
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101 
PA7I		__z8bit	IRQ1,7		;  Port A7 Interrupt Request
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PA6I		__z8bit	IRQ1,6		;  Port A6 Interrupt Request
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PA5I		__z8bit	IRQ1,5		;  Port A5 Interrupt Request
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PA4I		__z8bit	IRQ1,4		;  Port A4 Interrupt Request
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PA3I		__z8bit	IRQ1,3		;  Port A3 Interrupt Request
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PA2I		__z8bit	IRQ1,2		;  Port A2 Interrupt Request
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PA1I		__z8bit	IRQ1,1		;  Port A1 Interrupt Request
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PA0I		__z8bit	IRQ1,0		;  Port A0 Interrupt Request
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PA7ENH		__z8bit	IRQ1ENH,7	;  Port A7 Interrupt Enable & Priority
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PA7ENL		__z8bit	IRQ1ENL,7
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PA6ENH		__z8bit	IRQ1ENH,6	;  Port A6 Interrupt Enable & Priority
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PA6ENL		__z8bit	IRQ1ENL,6
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PA5ENH		__z8bit	IRQ1ENH,5	;  Port A5 Interrupt Enable & Priority
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PA5ENL		__z8bit	IRQ1ENL,5
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PA4ENH		__z8bit	IRQ1ENH,4	;  Port A4 Interrupt Enable & Priority
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PA4ENL		__z8bit	IRQ1ENL,4
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PA3ENH		__z8bit	IRQ1ENH,3	;  Port A3 Interrupt Enable & Priority
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PA3ENL		__z8bit	IRQ1ENL,3
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PA2ENH		__z8bit	IRQ1ENH,2	;  Port A2 Interrupt Enable & Priority
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PA2ENL		__z8bit	IRQ1ENL,2
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PA1ENH		__z8bit	IRQ1ENH,1	;  Port A1 Interrupt Enable & Priority
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PA1ENL		__z8bit	IRQ1ENL,1
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PA0ENH		__z8bit	IRQ1ENH,0	;  Port A0 Interrupt Enable & Priority
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PA0ENL		__z8bit	IRQ1ENL,0
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127 
PC3I		__z8bit	IRQ2,3		;  Port C3 Interrupt Request
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PC2I		__z8bit	IRQ2,2		;  Port C2 Interrupt Request
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PC1I		__z8bit	IRQ2,1		;  Port C1 Interrupt Request
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PC0I		__z8bit	IRQ2,0		;  Port C0 Interrupt Request
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C3ENH		__z8bit	IRQ2ENH,3	;  Port C3 Interrupt Enable & Priority
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C3ENL		__z8bit	IRQ2ENL,3
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C2ENH		__z8bit	IRQ2ENH,2	;  Port C2 Interrupt Enable & Priority
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C2ENL		__z8bit	IRQ2ENL,2
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C1ENH		__z8bit	IRQ2ENH,1	;  Port C1 Interrupt Enable & Priority
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C1ENL		__z8bit	IRQ2ENL,1
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C0ENH		__z8bit	IRQ2ENH,0	;  Port C0 Interrupt Enable & Priority
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C0ENL		__z8bit	IRQ2ENL,0
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141 
IRQES		sfr	0fcdh		; Interrupt Edge Select
142 
IRQCTL		sfr	0fcfh		; Interrupt Control
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IRQE		__z8bit	IRQCTL,7	;  Interrupt Request Enable
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145 
;----------------------------------------------------------------------------
146 
; Flash Memory Control
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148 
FCTL		sfr	0ff8h		; Flash Control
149 
FCMD		__z8bfield FCTL,0,8	;  Flash Command
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FSTAT		sfr	0ff8h		; Flash Status
151 
FPS		sfr	0ff9h		; Flash Page Select
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INFO_EN		__z8bit	FPS,7		;  Information Area Enable
153 
PAGE		__z8bfield FPS,0,7	;  Page Select
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FPROT		sfr	0ff9h		; Flash Sector Protect
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FFREQH		sfr	0ffah		; Flash Programming Frequency High Byte
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FFREQL		sfr	0ffbh		; Flash Programming Frequency Low Byte
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FFREQ		sfr	FFREQH
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159 
;----------------------------------------------------------------------------
160 
; GPIO
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162 
		__defgpio "A",0fd0h
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		__defgpio "B",0fd4h
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		__defgpio "C",0fd8h
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166 
;----------------------------------------------------------------------------
167 
; Timer
168 
 
169 
		__deftimer "0",0f00h,0,1
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		__deftimer "1",0f08h,0,1
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172 
;----------------------------------------------------------------------------
173 
; UART
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175 
		__defuart "0",0f40h
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177 
;----------------------------------------------------------------------------
178 
; I2C
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180 
		__defi2c 0f50h
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182 
;----------------------------------------------------------------------------
183 
; SPI
184 
 
185 
		__defspi 0f60h
186 
 
187 
;----------------------------------------------------------------------------
188 
; Analog/Digital Converter
189 
 
190 
		if	__hasadc
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ADCCTL		sfr	0f70h		; ADC Control 0
192 
CEN		__z8bit	ADCCTL,7	;  Conversion Enable
193 
VREF		__z8bit	ADCCTL,5	;  Voltage Reference
194 
CONT		__z8bit ADCCTL,4	;  Continuous Conversion
195 
ANAIN		__z8bfield ADCCTL,0,3	;  Analog Input Select
196 
ADCD_H		sfr	0f72h		; ADC Data High Byte
197 
ADCD_L		sfr	0f73h		; ADC Data Low Bits
198 
OVF		__z8bit	ADCD_L,0	;  Overflow Status
199 
ADCD		sfr	ADCD_H
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ADCSST		sfr	0f74h		; ADC Sample Settling Time
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SST		__z8bfield ADCSST,0,3	;  Sample Settling Time
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ADCST		sfr	0f75h		; ADC sample time
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ST		__z8bfield ADCST,0,6	;  Sample Time
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		endif			; __hasadc
205 
 
206 
;----------------------------------------------------------------------------
207 
; Watchdog Timer
208 
 
209 
WDTCTL		sfr	0ff0h		; Watchdog Timer Control
210 
WDTU		sfr	0ff1h		; Watchdog Timer Reload Upper Byte
211 
WDTH		sfr	0ff2h		; Watchdog Timer Reload High Byte
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WDTL		sfr	0ff3h		; Watchdog Timer Reload Low Byte
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214 
;----------------------------------------------------------------------------
215 
 
216 
		restore
217 
 
218 
		endif			; __regf0822inc