Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1186 | savelij | 1 | cpu 80960 |
| 2 | fpu on |
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| 3 | |||
| 4 | ; Data registers are 'ordered'. |
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| 5 | ; Registers 0, 1, 2, and 31 are equal to pfp, sp, rip and fp: |
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| 6 | |||
| 7 | db r4 == g2 ; 0 |
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| 8 | db r4 <> g2 ; 1 |
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| 9 | db r4 <= g2 ; 1 |
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| 10 | db r4 < g2 ; 1 |
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| 11 | db r4 >= g2 ; 0 |
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| 12 | db r4 > g2 ; 0 |
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| 13 | |||
| 14 | db r1 == sp ; 1 |
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| 15 | db r1 <> sp ; 0 |
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| 16 | db r1 <= sp ; 1 |
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| 17 | db r1 < sp ; 0 |
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| 18 | db r1 >= sp ; 1 |
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| 19 | db r1 > sp ; 0 |
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| 20 | |||
| 21 | ; Floating point registers are in a different 'dimension', so there is |
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| 22 | ; no lesser/greater: |
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| 23 | |||
| 24 | db fp2 == r2 ; 0 |
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| 25 | db fp2 <> r2 ; 1 |
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| 26 | db fp2 <= r2 ; 0 |
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| 27 | db fp2 < r2 ; 0 |
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| 28 | db fp2 >= r2 ; 0 |
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| 29 | db fp2 > r2 ; 0 |