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Rev | Author | Line No. | Line |
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151 | dimkam | 1 | |
2 | #define BYTE unsigned char |
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3 | #define WORD unsigned short |
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4 | #define ISO_BIT 0x10 |
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5 | #define MAX_EP 0x05 // maximum number of endpoints (Ep0 + max of 4 data endpoints) |
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6 | |||
7 | //***************************************************************************************** |
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8 | // Constant Defines |
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9 | //***************************************************************************************** |
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10 | |||
11 | #define TIMEOUT_RETRY 0x06 // Maximum no. of timeout retry during USB xfer |
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12 | |||
13 | typedef struct |
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14 | { |
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15 | WORD wVID, wPID; // Vendor ID and Product ID |
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16 | BYTE bClass; // |
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17 | BYTE bNumOfEPs; // actual number endpoint from slave |
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18 | BYTE iMfg; // Manufacturer ID |
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19 | BYTE iPdt; // Product ID |
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20 | BYTE bId1; |
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21 | BYTE bId2; |
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22 | BYTE bEPAddr[MAX_EP]; // bit 7 = 1 = use PID_IN, |
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23 | BYTE bAttr[MAX_EP]; // ISO | Bulk | Interrupt | Control |
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24 | WORD wPayLoad[MAX_EP]; // ISO range: 1-1023, Bulk: 1-64, etc |
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25 | WORD bInterval[MAX_EP]; // polling interval (for LS) |
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26 | BYTE bData1[MAX_EP]; // DataToggle value |
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27 | } pUSBDEV; |
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28 | |||
29 | typedef struct |
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30 | { |
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31 | BYTE bmRequest; |
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32 | BYTE bRequest; |
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33 | WORD wValue; |
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34 | WORD wIndex; |
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35 | WORD wLength; |
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36 | } SetupPKG; |
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37 | |||
38 | typedef struct |
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39 | { |
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40 | unsigned char usbaddr; |
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41 | unsigned char endpoint; |
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42 | unsigned char pid; |
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43 | unsigned char wPayload; |
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44 | unsigned int wLen; |
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45 | unsigned char *buffer; |
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46 | SetupPKG setup; |
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47 | unsigned char epbulkin; |
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48 | unsigned char epbulkout; |
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49 | |||
50 | } PKG; |
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51 | |||
52 | //------------------------------------------------------------------------ |
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53 | // EP0 use for configuration and Vendor Specific command interface |
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54 | //------------------------------------------------------------------------ |
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55 | #define EP0_Buf 0x10 // define start of EP0 64-byte buffer |
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56 | #define EP1_Buf 0x40 // define start of EP1 64-byte buffer |
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57 | |||
58 | /*------------------------------------------------------------------------- |
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59 | * SL811H Register Control memory map |
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60 | * --Note: |
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61 | * --SL11H only has one control register set from 0x00-0x04 |
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62 | * --SL811H has two control register set from 0x00-0x04 and 0x08-0x0c |
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63 | *------------------------------------------------------------------------*/ |
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64 | |||
65 | #define EP0Control 0x00 |
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66 | #define EP0Address 0x01 |
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67 | #define EP0XferLen 0x02 |
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68 | #define EP0Status 0x03 |
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69 | #define EP0Counter 0x04 |
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70 | |||
71 | #define EP1Control 0x08 |
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72 | #define EP1Address 0x09 |
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73 | #define EP1XferLen 0x0a |
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74 | #define EP1Status 0x0b |
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75 | #define EP1Counter 0x0c |
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76 | |||
77 | #define CtrlReg 0x05 |
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78 | #define IntEna 0x06 |
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79 | // 0x07 is reserved |
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80 | #define IntStatus 0x0d |
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81 | #define cDATASet 0x0e |
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82 | #define cSOFcnt 0x0f // Master=1 Slave=0, D+/D-Pol Swap=1 0=not [0-5] SOF Count |
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83 | // 0xAE = 1100 1110 |
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84 | // 0xEE = 1110 1110 |
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85 | |||
86 | #define IntMask 0x57 /* Reset|DMA|EP0|EP2|EP1 for IntEna */ |
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87 | #define HostMask 0x47 /* Host request command for IntStatus */ |
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88 | #define ReadMask 0xd7 /* Read mask interrupt for IntStatus */ |
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89 | |||
90 | //Interrupt Status Mask |
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91 | #define USB_A_DONE 0x01 |
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92 | #define USB_B_DONE 0x02 |
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93 | #define BABBLE_DETECT 0x04 |
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94 | #define INT_RESERVE 0x08 |
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95 | #define SOF_TIMER 0x10 |
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96 | #define INSERT_REMOVE 0x20 |
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97 | #define USB_RESET 0x40 |
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98 | #define USB_DPLUS 0x80 |
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99 | #define INT_CLEAR 0xFF |
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100 | |||
101 | //EP0 Status Mask |
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102 | #define EP0_ACK 0x01 // EPxStatus bits mask during a read |
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103 | #define EP0_ERROR 0x02 |
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104 | #define EP0_TIMEOUT 0x04 |
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105 | #define EP0_SEQUENCE 0x08 |
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106 | #define EP0_SETUP 0x10 |
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107 | #define EP0_OVERFLOW 0x20 |
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108 | #define EP0_NAK 0x40 |
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109 | #define EP0_STALL 0x80 |
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110 | |||
111 | /*------------------------------------------------------------------------- |
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112 | * Standard Chapter 9 definition |
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113 | *------------------------------------------------------------------------- |
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114 | */ |
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115 | #define GET_STATUS 0x00 |
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116 | #define CLEAR_FEATURE 0x01 |
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117 | #define SET_FEATURE 0x03 |
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118 | #define SET_ADDRESS 0x05 |
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119 | #define GET_DESCRIPTOR 0x06 |
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120 | #define SET_DESCRIPTOR 0x07 |
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121 | #define GET_CONFIG 0x08 |
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122 | #define SET_CONFIG 0x09 |
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123 | #define GET_INTERFACE 0x0a |
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124 | #define SET_INTERFACE 0x0b |
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125 | #define SYNCH_FRAME 0x0c |
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126 | |||
127 | |||
128 | #define DEVICE 0x01 |
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129 | #define CONFIGURATION 0x02 |
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130 | #define STRING 0x03 |
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131 | #define INTERFACE 0x04 |
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132 | #define ENDPOINT 0x05 |
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133 | |||
134 | #define STDCLASS 0x00 |
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135 | |||
136 | /*------------------------------------------------------------------------- |
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137 | * SL11H/SL811H definition |
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138 | *------------------------------------------------------------------------- |
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139 | */ |
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140 | |||
141 | // USB-A, USB-B Host Control Register [00H, 08H] |
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142 | // Pre Reserved |
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143 | // DatT Dir [1=Trans, 0=Recv] |
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144 | // SOF Enable |
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145 | // ISO Arm |
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146 | #define DATA0_WR 0x07 // 0000 0111 ( Data0 + OUT + Enable + Arm) |
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147 | #define sDATA0_WR 0x27 // 0010 0111 ( Data0 + SOF + OUT + Enable + Arm) |
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148 | |||
149 | #define DATA0_RD 0x03 // 0000 0011 ( Data0 + IN + Enable + Arm) |
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150 | #define sDATA0_RD 0x23 // 0010 0011 ( Data0 + SOF + IN + Enable + Arm) |
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151 | |||
152 | #define PID_SETUP 0xD0 |
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153 | #define PID_IN 0x90 |
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154 | #define PID_OUT 0x10 |
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155 | |||
156 | |||
157 | unsigned char SL811_GetRev(void); |
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158 | void USBReset(void); |
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159 | unsigned char usbXfer(void); |
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160 | unsigned char ep0Xfer(void); |
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161 | unsigned char epBulkSend(unsigned char *pBuffer,unsigned int len); |
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162 | unsigned char epBulkRcv(unsigned char *pBuffer,unsigned int len); |
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163 | unsigned char SetAddress(unsigned char addr); |
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164 | unsigned char Set_Configuration(void); |
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165 | |||
166 | unsigned char EnumUsbDev(BYTE usbaddr); |
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167 | void SL811_Init(void); |
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168 | |||
169 | //void check_key_LED(void); |