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64 ddp 1
// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module lpm_rom0 (
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        address,
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        q);
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        input   [9:0]  address;
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        output  [7:0]  q;
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        wire [7:0] sub_wire0;
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        wire [7:0] q = sub_wire0[7:0];
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        lpm_rom lpm_rom_component (
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                                .address (address),
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                                .q (sub_wire0),
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                                .inclock (1'b1),
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                                .memenab (1'b1),
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                                .outclock (1'b1));
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        defparam
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                lpm_rom_component.intended_device_family = "ACEX1K",
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                lpm_rom_component.lpm_address_control = "UNREGISTERED",
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                lpm_rom_component.lpm_file = "ZX_FONT.HEX",
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                lpm_rom_component.lpm_outdata = "UNREGISTERED",
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                lpm_rom_component.lpm_type = "LPM_ROM",
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                lpm_rom_component.lpm_width = 8,
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                lpm_rom_component.lpm_widthad = 10;
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endmodule