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Rev | Author | Line No. | Line |
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334 | lvd | 1 | `include "../include/tune.v" |
333 | lvd | 2 | |
334 | lvd | 3 | // Pentevo project (c) NedoPC 2011 |
4 | // |
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5 | // fetches video data for renderer |
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6 | |||
7 | module video_fetch( |
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8 | |||
9 | input wire clk, // 28 MHz clock |
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10 | |||
11 | |||
12 | input wire cend, // general |
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13 | input wire pre_cend, // synchronization |
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14 | |||
333 | lvd | 15 | input wire vpix, // vertical window |
334 | lvd | 16 | |
17 | input wire fetch_start, // fetching start and stop |
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18 | input wire fetch_end, // |
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19 | |||
336 | lvd | 20 | output reg fetch_sync, // 1 cycle after cend |
334 | lvd | 21 | |
22 | |||
23 | input wire [15:0] video_data, // video data receiving from dram arbiter |
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24 | input wire video_strobe, // |
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25 | output reg video_go, // indicates need for data |
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26 | |||
336 | lvd | 27 | output reg [63:0] pic_bits // picture bits -- data for renderer |
334 | lvd | 28 | |
29 | // currently, video_fetch assigns that there are only 1/8 and 1/4 |
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30 | // bandwidth. !!needs correction for higher bandwidths!! |
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31 | |||
32 | |||
33 | ); |
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34 | reg [3:0] fetch_sync_ctr; // generates fetch_sync to synchronize |
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35 | // fetch cycles (each 16 dram cycles long) |
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36 | // fetch_sync coincides with cend |
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37 | |||
38 | reg [1:0] fetch_ptr; // pointer to fill pic_bits buffer |
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39 | reg fetch_ptr_clr; // clears fetch_ptr |
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40 | |||
41 | |||
42 | reg [15:0] fetch_data [0:3]; // stores data fetched from memory |
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43 | |||
44 | // fetch window |
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45 | always @(posedge clk) |
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46 | if( fetch_start && vpix ) |
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47 | video_go <= 1'b1; |
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48 | else if( fetch_end ) |
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49 | video_go <= 1'b0; |
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50 | |||
51 | |||
52 | |||
53 | // fetch sync counter |
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330 | lvd | 54 | always @(posedge clk) if( cend ) |
334 | lvd | 55 | begin |
56 | if( fetch_start ) |
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57 | fetch_sync_ctr <= 0; |
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58 | else |
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59 | fetch_sync_ctr <= fetch_sync_ctr + 1; |
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330 | lvd | 60 | end |
334 | lvd | 61 | |
62 | |||
63 | // fetch sync signal |
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64 | always @(posedge clk) |
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339 | lvd | 65 | if( (fetch_sync_ctr==1) && pre_cend ) |
334 | lvd | 66 | fetch_sync <= 1'b1; |
67 | else |
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68 | fetch_sync <= 1'b0; |
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69 | |||
70 | |||
335 | lvd | 71 | |
334 | lvd | 72 | // fetch_ptr clear signal |
73 | always @(posedge clk) |
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74 | if( (fetch_sync_ctr==0) && pre_cend ) |
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75 | fetch_ptr_clr <= 1'b1; |
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76 | else |
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77 | fetch_ptr_clr <= 1'b0; |
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78 | |||
79 | |||
80 | // buffer fill pointer |
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81 | always @(posedge clk) |
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82 | if( fetch_ptr_clr ) |
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83 | fetch_ptr <= 0; |
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84 | else if( video_strobe ) |
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85 | fetch_ptr <= fetch_ptr + 1; |
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86 | |||
87 | |||
88 | |||
89 | // store fetched data |
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90 | always @(posedge clk) if( video_strobe ) |
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91 | fetch_data[fetch_ptr] <= video_data; |
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92 | |||
339 | lvd | 93 | |
334 | lvd | 94 | // pass fetched data to renderer |
336 | lvd | 95 | always @(posedge clk) if( fetch_sync ) |
334 | lvd | 96 | begin |
97 | pic_bits[ 7:0 ] <= fetch_data[0][15:8 ]; |
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98 | pic_bits[15:8 ] <= fetch_data[0][ 7:0 ]; |
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99 | pic_bits[23:16] <= fetch_data[1][15:8 ]; |
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100 | pic_bits[31:24] <= fetch_data[1][ 7:0 ]; |
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101 | pic_bits[39:32] <= fetch_data[2][15:8 ]; |
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102 | pic_bits[47:40] <= fetch_data[2][ 7:0 ]; |
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103 | pic_bits[55:48] <= fetch_data[3][15:8 ]; |
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104 | pic_bits[63:56] <= fetch_data[3][ 7:0 ]; |
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105 | end |
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106 | |||
107 | endmodule |
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108 | |||
109 |