WebSVN – ngs – Blame – /z80/bootFPGA00/bootFPGA.asm

Rev	Author	Line No.	Line
4	lvd	1	; Part of NeoGS project, (c) NedoPC 2007-2008
		2	;
		3	; FPGA boot
		4	;
		5	;
		6	include "cpld_ports.inc"
		7
		8	relaxed on
		9
		10	ORG 0
		11	phase 0
		12
		13	stack_top equ 0x4080
		14	recode_tbl equ 0x4100
		15
		16	wbuf_addr equ 0x6000 ;8kB buffer, 8kb boundary
		17	wbuf_size equ 0x2000
		18	wbuf_hsize equ wbuf_size>>8
		19	wbuf_mask equ 1fffh
		20	wbuf_hmask equ wbuf_mask>>8
		21	wbuf_hend equ (wbuf_addr+wbuf_size)>>8
		22
		23
		24
		25	di
		26	di
		27	jr LOAD
		28
		29	jp (ix)
		30	jp (ix)
		31
		32	ret
		33	ret
		34	ret
		35	ret
		36
		37	di
		38	halt
		39	di
		40	halt
		41
		42	DEF_ROM:
		43	di ;for default ROM load
		44	ld sp,stack_top
		45	call prepare
		46	jr ROM
		47
		48	LOAD:
		49	ld sp,stack_top ; use for stack first 128 bytes of RAM
		50
		51	call prepare
		52
		53
		54	in a,(C_CRES)
		55	rlca
		56	jr c,TRY_RAM
		57	ROM:
		58	xor a
		59	out (C_MCFG),a
67	lvd	60	ld hl,config_data+0x8000
4	lvd	61	jr loadconfig
		62
		63	TRY_RAM:
		64	ld a,0x81
		65	out (C_MCFG),a ;ram at 8000-FFFF, page 1
		66
		67	ld hl,0x8000
		68	ld b,(hl)
		69	inc l
		70	ld c,(hl)
		71	inc l
		72
		73	ld a,b
		74	or a
		75	jr z,ROM ;$0100 min length!
		76	cp 0x7F
		77	jr nc,ROM ;$7EFF max length!
		78
		79	add hl,bc
		80
		81	ld d,(hl) ;precomputed CRC value
		82	dec (hl) ;KILL CRC
		83	inc hl
		84	ld e,(hl)
		85	inc (hl) ;KILL CRC
		86	push de
		87
		88	inc bc
		89	inc bc
		90	ld hl,0x8000
		91	call CRC16
		92
		93	pop hl
		94	or a
		95	sbc hl,de
		96	jr nz,ROM ;if CRC failed
		97
		98	ld hl,0x8002
		99
		100	;; start configuration
		101	loadconfig:
		102	ld a,0x81
		103	out (C_CRNCFG),a ;clear cold_reset flag
		104	call configure
		105
		106	; end config, see is it correct
		107	wait_init:
		108	in a,(C_NSTCDON)
		109	sra a
		110	jp p,DEF_ROM
		111	jr nc,wait_init
		112
		113	; here CONF_DONE is released, nothing to do more (reboot takes place when INIT_DONE toggles)
		114
		115	di
		116	halt
		117
		118
		119
		120	USE_BUFFER: ;hl - from
		121	;de - len (down to zero)
		122	;kills af,bc,de,hl
		123
		124	ld b,recode_tbl>>8
		125	jr ub_entry
		126
		127	ub_loop:
		128	ld c,(hl)
		129	inc hl
		130	ld a,(bc)
		131	out (C_FPGADAT),a
		132
		133
		134	call ready
		135
		136
		137	dec de
		138
		139	ub_entry: ld a,d
		140	or e
		141	jr nz,ub_loop
		142
		143	ret
		144
		145
		146	prepare:
		147	;reset FPGA by pulling NCONFIG down
		148	xor a
		149	out (C_CRNCFG),a
		150
67	lvd	151	;switch ROM in 8000-FFFF, first 32k, then check it for CRC
		152	;xor a
		153	out (C_MCFG),a
		154
4	lvd	155	;calc and compare CRC of rom
67	lvd	156	ld hl,0x8000
4	lvd	157	ld bc,crc_is_here
		158	call CRC16
		159	ld a,(hl)
		160	inc hl
		161	ld l,(hl)
		162	ld h,a
		163	or a
		164	sbc hl,de
		165	jr nz,prepare
		166
		167	call mk_recode_tbl
		168
		169	ld a,1
		170	out (C_CRNCFG),a ;release nconfig
		171
		172	wait_nstat:
		173	in a,(C_NSTCDON) ;read nstatus, wait it to be 1
		174	rla
		175	jr nc,wait_nstat
		176
		177	ret
		178
		179
		180	ready:
		181
		182	cfg_rdynbsy: ; wait for ready
		183	in a,(C_FPGADAT)
		184	rla
		185	jr nc,cfg_rdynbsy
		186
		187	; restart if error during configuration
		188	in a,(C_NSTCDON)
		189	rla
		190	jp nc,DEF_ROM
		191
		192	ret
		193
		194
		195
		196	mk_recode_tbl:
		197	ld de,recode_tbl
		198	mrt_loop:
		199
		200	ld a,e
		201	and 0b01001001 ; preserve d0,d3,d6
		202	ld b,a
		203
		204	ld a,e
		205	and 0b10010000 ; d7 and d4
		206	rrca
		207	rrca
		208	rrca
		209	or b
		210	ld b,a ;01011011
		211
		212	ld a,e
		213	and 0b00000010 ; d1
		214	rlca
		215	or b
		216	ld b,a ;01011111
		217
		218	ld a,e
		219	and 0b00000100 ; d2
		220	rlca
		221	rlca
		222	rlca
		223	or b
		224	ld b,a ;01111111
		225
		226	ld a,e
		227	and 0b00100000 ; d5
		228	rlca
		229	rlca
		230	or b ;11111111
		231
		232	ld (de),a
		233
		234	inc e
		235	jr nz,mrt_loop
		236
		237	ret
		238
		239	;; recode config data:
		240
		241	; Z80 fpga
		242	; D0 D0 *
		243	; D1 D4
		244	; D2 D1
		245	; D3 D3 *
		246	; D4 D7
		247	; D5 D2
		248	; D6 D6 *
		249	; D7 D5
		250
		251
		252
		253	configure:
		254	ld de,wbuf_addr
		255
		256	DEC40buf
		257	LD A,0x80
		258	EX AF,AF'
		259	MS LDI
		260	call after_ldi
		261	M0 LD BC,0x2FF
		262	M1 EX AF,AF'
		263	M1X ADD A,A
		264	JR NZ,M2
		265	LD A,(HL)
		266	INC HL
		267	RLA
		268	M2 RL C
		269	JR NC,M1X
		270	EX AF,AF'
		271	DJNZ X2
		272	LD A,2
		273	SRA C
		274	JR C,N1
		275	INC A
		276	INC C
		277	JR Z,N2
		278	LD BC,0x33F
		279	JR M1
		280
		281	X2 DJNZ X3
		282	SRL C
		283	JR C,MS
		284	INC B
		285	JR M1
		286	X6
		287	ADD A,C
		288	N2
		289	LD BC,0x4FF
		290	JR M1
		291	N1
		292	INC C
		293	JR NZ,M4
		294	EX AF,AF'
		295	INC B
		296	N5 RR C
		297	;;;; RET C
		298	jr c,dec40end
		299
		300	RL B
		301	ADD A,A
		302	JR NZ,N6
		303	LD A,(HL)
		304	INC HL
		305	RLA
		306	N6 JR NC,N5
		307	EX AF,AF'
		308	ADD A,B
		309	LD B,6
		310	JR M1
		311	X3
		312	DJNZ X4
		313	LD A,1
		314	JR M3
		315	X4 DJNZ X5
		316	INC C
		317	JR NZ,M4
		318	LD BC,0x51F
		319	JR M1
		320	X5
		321	DJNZ X6
		322	LD B,C
		323	M4 LD C,(HL)
		324	INC HL
		325	M3 DEC B
		326	PUSH HL
		327	LD L,C
		328	LD H,B
		329	ADD HL,DE
		330	LD C,A
		331	LD B,0
		332	;;;; LDIR
		333	call wrap_ldir
		334	POP HL
		335	JR M0
		336	END_DEC40
		337
		338	dec40end:
		339	ex de,hl
		340	ld de,wbuf_addr
		341	or a
		342	sbc hl,de
		343	ex de,hl
		344	jp USE_BUFFER
		345
		346
		347	after_ldi: push af
		348	ld a,d
		349	cp wbuf_hend
		350	jr c,al_nothing
		351	push hl
		352
		353	ld hl,wbuf_addr
		354	ld de,0x2000
		355	call USE_BUFFER
		356
		357	ld de,wbuf_addr
		358	pop hl
		359	al_nothing:
		360	pop af
		361	ret
		362
		363
		364	wrap_ldir:
		365	ld a,h
		366	cp wbuf_addr>>8
		367	jr nc,wl_nohlwrap
		368	add a,wbuf_hsize
		369	ld h,a
		370	wl_nohlwrap:
		371	ld a,wbuf_hend-1
		372	wl_ldiloop:
		373	ldi
		374	jp po,after_ldi
		375
		376	cp d
		377	jr c,wl_dewrap
		378	cp h
		379	jr nc,wl_ldiloop
		380	;wl_hlwrap
		381	ld h,wbuf_addr>>8
		382	jr wl_ldiloop
		383	wl_dewrap:
		384	push bc
		385	call after_ldi
		386	pop bc
		387	jr wl_nohlwrap
		388
		389
		390
		391
		392	CRC16: ;calculates crc16-ccitt with initial value of CRC=$FFFF
		393
		394	;INPUT: HL - memptr
		395	; BC - byte count
		396	;OUTPUT: DE - resulting crc value
		397	; HL - ptr to byte after last processed
		398	;KILLS: AF,BC,IX
		399
		400	;algo: crc = (crc<<8) ^ crc16tab[((crc>>8) ^ (char )buf++)&0x00FF];
		401
		402	ld a,c
		403	or a
		404	jr z,$+3
		405	inc b
		406
		407	ld ixl,b
		408	ld b,c
		409
		410
		411	ex de,hl
		412	ld hl,(crc16table&$FF00)+$FF ;high part of table, initial crc.lo
		413	ld c,l ;initial crc.hi
		414
		415	c1_loop
		416
		417	;de - memptr; h - table>>8, c - crc.hi, l - crc.lo, b - counter
		418
		419	ld a,(de)
		420	inc de
		421	xor c
		422	ld c,a ;c=index
		423
		424	ld a,l ;a=crc.lo
		425	ld l,c ;hl=tab.hi
		426	xor (hl) ;a=new crc.hi
		427	inc h
		428	ld l,(hl) ;l=new crc.lo
		429	dec h
		430	ld c,a
		431
		432	djnz c1_loop
		433
		434	dec ixl
		435	jr nz,c1_loop
		436
		437
		438	ld h,c
		439	ex de,hl
		440
		441	ret
		442
		443
		444
		445	org ($+255)&0xFF00
		446	crc16table:
		447	db 0x00,0x10,0x20,0x30,0x40,0x50,0x60,0x70
		448	db 0x81,0x91,0xa1,0xb1,0xc1,0xd1,0xe1,0xf1
		449	db 0x12,0x02,0x32,0x22,0x52,0x42,0x72,0x62
		450	db 0x93,0x83,0xb3,0xa3,0xd3,0xc3,0xf3,0xe3
		451	db 0x24,0x34,0x04,0x14,0x64,0x74,0x44,0x54
		452	db 0xa5,0xb5,0x85,0x95,0xe5,0xf5,0xc5,0xd5
		453	db 0x36,0x26,0x16,0x06,0x76,0x66,0x56,0x46
		454	db 0xb7,0xa7,0x97,0x87,0xf7,0xe7,0xd7,0xc7
		455	db 0x48,0x58,0x68,0x78,0x08,0x18,0x28,0x38
		456	db 0xc9,0xd9,0xe9,0xf9,0x89,0x99,0xa9,0xb9
		457	db 0x5a,0x4a,0x7a,0x6a,0x1a,0x0a,0x3a,0x2a
		458	db 0xdb,0xcb,0xfb,0xeb,0x9b,0x8b,0xbb,0xab
		459	db 0x6c,0x7c,0x4c,0x5c,0x2c,0x3c,0x0c,0x1c
		460	db 0xed,0xfd,0xcd,0xdd,0xad,0xbd,0x8d,0x9d
		461	db 0x7e,0x6e,0x5e,0x4e,0x3e,0x2e,0x1e,0x0e
		462	db 0xff,0xef,0xdf,0xcf,0xbf,0xaf,0x9f,0x8f
		463	db 0x91,0x81,0xb1,0xa1,0xd1,0xc1,0xf1,0xe1
		464	db 0x10,0x00,0x30,0x20,0x50,0x40,0x70,0x60
		465	db 0x83,0x93,0xa3,0xb3,0xc3,0xd3,0xe3,0xf3
		466	db 0x02,0x12,0x22,0x32,0x42,0x52,0x62,0x72
		467	db 0xb5,0xa5,0x95,0x85,0xf5,0xe5,0xd5,0xc5
		468	db 0x34,0x24,0x14,0x04,0x74,0x64,0x54,0x44
		469	db 0xa7,0xb7,0x87,0x97,0xe7,0xf7,0xc7,0xd7
		470	db 0x26,0x36,0x06,0x16,0x66,0x76,0x46,0x56
		471	db 0xd9,0xc9,0xf9,0xe9,0x99,0x89,0xb9,0xa9
		472	db 0x58,0x48,0x78,0x68,0x18,0x08,0x38,0x28
		473	db 0xcb,0xdb,0xeb,0xfb,0x8b,0x9b,0xab,0xbb
		474	db 0x4a,0x5a,0x6a,0x7a,0x0a,0x1a,0x2a,0x3a
		475	db 0xfd,0xed,0xdd,0xcd,0xbd,0xad,0x9d,0x8d
		476	db 0x7c,0x6c,0x5c,0x4c,0x3c,0x2c,0x1c,0x0c
		477	db 0xef,0xff,0xcf,0xdf,0xaf,0xbf,0x8f,0x9f
		478	db 0x6e,0x7e,0x4e,0x5e,0x2e,0x3e,0x0e,0x1e
		479
		480	db 0x00,0x21,0x42,0x63,0x84,0xa5,0xc6,0xe7
		481	db 0x08,0x29,0x4a,0x6b,0x8c,0xad,0xce,0xef
		482	db 0x31,0x10,0x73,0x52,0xb5,0x94,0xf7,0xd6
		483	db 0x39,0x18,0x7b,0x5a,0xbd,0x9c,0xff,0xde
		484	db 0x62,0x43,0x20,0x01,0xe6,0xc7,0xa4,0x85
		485	db 0x6a,0x4b,0x28,0x09,0xee,0xcf,0xac,0x8d
		486	db 0x53,0x72,0x11,0x30,0xd7,0xf6,0x95,0xb4
		487	db 0x5b,0x7a,0x19,0x38,0xdf,0xfe,0x9d,0xbc
		488	db 0xc4,0xe5,0x86,0xa7,0x40,0x61,0x02,0x23
		489	db 0xcc,0xed,0x8e,0xaf,0x48,0x69,0x0a,0x2b
		490	db 0xf5,0xd4,0xb7,0x96,0x71,0x50,0x33,0x12
		491	db 0xfd,0xdc,0xbf,0x9e,0x79,0x58,0x3b,0x1a
		492	db 0xa6,0x87,0xe4,0xc5,0x22,0x03,0x60,0x41
		493	db 0xae,0x8f,0xec,0xcd,0x2a,0x0b,0x68,0x49
		494	db 0x97,0xb6,0xd5,0xf4,0x13,0x32,0x51,0x70
		495	db 0x9f,0xbe,0xdd,0xfc,0x1b,0x3a,0x59,0x78
		496	db 0x88,0xa9,0xca,0xeb,0x0c,0x2d,0x4e,0x6f
		497	db 0x80,0xa1,0xc2,0xe3,0x04,0x25,0x46,0x67
		498	db 0xb9,0x98,0xfb,0xda,0x3d,0x1c,0x7f,0x5e
		499	db 0xb1,0x90,0xf3,0xd2,0x35,0x14,0x77,0x56
		500	db 0xea,0xcb,0xa8,0x89,0x6e,0x4f,0x2c,0x0d
		501	db 0xe2,0xc3,0xa0,0x81,0x66,0x47,0x24,0x05
		502	db 0xdb,0xfa,0x99,0xb8,0x5f,0x7e,0x1d,0x3c
		503	db 0xd3,0xf2,0x91,0xb0,0x57,0x76,0x15,0x34
		504	db 0x4c,0x6d,0x0e,0x2f,0xc8,0xe9,0x8a,0xab
		505	db 0x44,0x65,0x06,0x27,0xc0,0xe1,0x82,0xa3
		506	db 0x7d,0x5c,0x3f,0x1e,0xf9,0xd8,0xbb,0x9a
		507	db 0x75,0x54,0x37,0x16,0xf1,0xd0,0xb3,0x92
		508	db 0x2e,0x0f,0x6c,0x4d,0xaa,0x8b,0xe8,0xc9
		509	db 0x26,0x07,0x64,0x45,0xa2,0x83,0xe0,0xc1
		510	db 0x1f,0x3e,0x5d,0x7c,0x9b,0xba,0xd9,0xf8
		511	db 0x17,0x36,0x55,0x74,0x93,0xb2,0xd1,0xf0
		512
71	lvd	513
		514
		515
		516
		517	config_data:
		518	binclude "main.mlz"
		519
		520
4	lvd	521	crc_is_here:
		522

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(root)/z80/bootFPGA00/bootFPGA.asm – Rev 71