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old------^
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old------^
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state
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state
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access time for both sl811 and w5300 -- 5tc
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access time for both sl811 and w5300 -- 5tc
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data setup for w5300: 42ns
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data setup for sl811: 25..85ns
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READ: via latch, transparent during access time, then latches read data (if CPU cycle continues)
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READ: via latch, transparent during access time, then latches read data (if CPU cycle continues)
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WRITE: via latch, data latched from CPU early, shown to the peripherals for the 5 tc
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WRITE: via latch, data latched from CPU early, shown to the peripherals for the 5 tc
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 -- ACHTUNG write /WR strobe is late!!!111
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5tc@48MHz = 1.5 tc @ 14MHz
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4tc@48MHz = 1.2 tc @ 14MHz
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so write will finish after 2.7 tc @ 14MHz after write pulse begin (memory write),
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such write WON'T coincide with the following memory read cycle, because it can't start earlier than
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3tc @48MHz after read pulse
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TODO:
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 + забуферировать rd/wr
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 + забуферировать cs's
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 + забуферировать sl811_a0
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 + забуферировать w5300_a
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 + сделать новое управление шиной
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