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#include "rs232.h"
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#include "rs232.h"
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#include "rtc.h"
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#include "rtc.h"
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#include "atx.h"
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#include "atx.h"
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#include "joystick.h"
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#include "joystick.h"
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/** Pointer to current byte in FPGA. */
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/** FPGA data pointer [far address] (linker symbol). */
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extern ULONG fpga PROGMEM;
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// FPGA data index..
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ULONG curFpga;
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volatile ULONG curFpga;
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//Common flag register.
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// Common flag register.
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volatile UBYTE flags_register;
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volatile UBYTE flags_register;
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// Common modes register.
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// Common modes register.
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volatile UBYTE modes_register;
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volatile UBYTE modes_register;
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//buffer for depacking FPGA configuration
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// Buffer for depacking FPGA configuration.
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//you can USED for other purposed after setup FPGA
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// You can USED for other purposed after setup FPGA.
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UBYTE dbuf[DBSIZE];
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UBYTE dbuf[DBSIZE];
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void put_buffer(UWORD size)
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void put_buffer(UWORD size)
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{
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{
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        // writes specified length of buffer to the output
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        // writes specified length of buffer to the output
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        DDRF |= (1<<nCONFIG); // pull low for a time
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        DDRF |= (1<<nCONFIG); // pull low for a time
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        _delay_us(40);
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        _delay_us(40);
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        DDRF &= ~(1<<nCONFIG);
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        DDRF &= ~(1<<nCONFIG);
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        while( !(PINF & (1<<nSTATUS)) ); // wait ready
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        while( !(PINF & (1<<nSTATUS)) ); // wait ready
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        curFpga = fpga; // prepare for data fetching
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        curFpga = GET_FAR_ADDRESS(fpga); // prepare for data fetching
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#ifdef LOGENABLE
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        {
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        char log_fpga[]="F........\r\n";
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        UBYTE b = (UBYTE)((curFpga>>24)&0xFF);
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        log_fpga[1] = ((b >> 4) <= 9 )?'0'+(b >> 4):'A'+(b >> 4)-10;
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        log_fpga[2] = ((b & 0x0F) <= 9 )?'0'+(b & 0x0F):'A'+(b & 0x0F)-10;
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        b = (UBYTE)((curFpga>>16)&0xFF);
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        log_fpga[3] = ((b >> 4) <= 9 )?'0'+(b >> 4):'A'+(b >> 4)-10;
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        log_fpga[4] = ((b & 0x0F) <= 9 )?'0'+(b & 0x0F):'A'+(b & 0x0F)-10;
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        b = (UBYTE)((curFpga>>8)&0xFF);
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        log_fpga[5] = ((b >> 4) <= 9 )?'0'+(b >> 4):'A'+(b >> 4)-10;
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        log_fpga[6] = ((b & 0x0F) <= 9 )?'0'+(b & 0x0F):'A'+(b & 0x0F)-10;
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        b = (UBYTE)(curFpga&0xFF);
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        log_fpga[7] = ((b >> 4) <= 9 )?'0'+(b >> 4):'A'+(b >> 4)-10;
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        log_fpga[8] = ((b & 0x0F) <= 9 )?'0'+(b & 0x0F):'A'+(b & 0x0F)-10;
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        to_log(log_fpga);
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        }
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#endif
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        depacker_dirty();
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        depacker_dirty();
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        //power led OFF
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        //power led OFF
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        LED_PORT |= 1<<LED;
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        LED_PORT |= 1<<LED;
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        //INT7 - RTC  (falling edge)
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        //INT7 - RTC  (falling edge)
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        EICRB = (1<<ISC41)+(0<<ISC40) + (1<<ISC51)+(0<<ISC50) + (1<<ISC61)+(0<<ISC60) + (1<<ISC71)+(0<<ISC70); // set condition for interrupt
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        EICRB = (1<<ISC41)+(0<<ISC40) + (1<<ISC51)+(0<<ISC50) + (1<<ISC61)+(0<<ISC60) + (1<<ISC71)+(0<<ISC70); // set condition for interrupt
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        EIFR = (1<<INTF4)|(1<<INTF5)|(1<<INTF6)|(1<<INTF7); // clear spurious ints there
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        EIFR = (1<<INTF4)|(1<<INTF5)|(1<<INTF6)|(1<<INTF7); // clear spurious ints there
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        EIMSK |= (1<<INT4)|(1<<INT5)|(1<<INT6)|(1<<INT7); // enable
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        EIMSK |= (1<<INT4)|(1<<INT5)|(1<<INT6)|(1<<INT7); // enable
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        rtc_init();
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        zx_init();
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        zx_init();
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        rtc_init();
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#ifdef LOGENABLE
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#ifdef LOGENABLE
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        to_log("zx_init OK\r\n");
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        to_log("zx_init OK\r\n");
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#endif
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#endif