Rev 905 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 905 | Rev 983 | ||
|---|---|---|---|
| Line 119... | Line 119... | ||
| 119 | reg romnram; |
119 | reg romnram; |
| 120 | reg wrdisable; |
120 | reg wrdisable; |
| 121 | 121 | ||
| 122 | 122 | ||
| 123 | 123 | ||
| 124 | - | ||
| 125 | reg [15:0] rd_buf; |
- | |
| 126 | - | ||
| 127 | reg [15:1] cached_addr; |
- | |
| 128 | reg cached_addr_valid; |
- | |
| 129 | - | ||
| 130 | wire cache_hit; |
- | |
| 131 | - | ||
| 132 | - | ||
| 133 | wire dram_beg; |
124 | wire dram_beg; |
| 134 | wire opfetch, memrd, memwr; |
125 | wire opfetch, memrd, memwr; |
| 135 | wire stall14, stall7_35; |
126 | wire stall14, stall7_35; |
| 136 | 127 | ||
| 137 | wire stall14_ini; |
128 | wire stall14_ini; |
| Line 225... | Line 216... | ||
| 225 | 216 | ||
| 226 | 217 | ||
| 227 | assign zd_ena = (~mreq_n) & (~rd_n) & (~romnram); |
218 | assign zd_ena = (~mreq_n) & (~rd_n) & (~romnram); |
| 228 | 219 | ||
| 229 | 220 | ||
| - | 221 | wire code_cache_select; |
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| - | 222 | reg [15:1] code_cached_addr; |
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| - | 223 | reg code_cached_addr_valid; |
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| - | 224 | reg [15:0] code_cached_word; |
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| - | 225 | ||
| - | 226 | wire data_cache_select; |
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| - | 227 | reg [15:1] data_cached_addr; |
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| - | 228 | reg data_cached_addr_valid; |
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| - | 229 | reg [15:0] data_cached_word; |
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| 230 | 230 | ||
| - | 231 | wire cache_hit; |
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| 231 | assign cache_hit = ( (za[15:1] == cached_addr[15:1]) && cached_addr_valid ); |
232 | wire [15:0] selected_cache; |
| 232 | 233 | ||
| - | 234 | assign code_cache_select = (za[15:1] == code_cached_addr[15:1]); |
|
| - | 235 | assign data_cache_select = (za[15:1] == data_cached_addr[15:1]); |
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| 233 | 236 | ||
| - | 237 | assign cache_hit = (code_cache_select && code_cached_addr_valid) || (data_cache_select && data_cached_addr_valid); |
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| - | 238 | assign selected_cache = (data_cache_select && data_cached_addr_valid) ? data_cached_word : code_cached_word; |
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| 234 | 239 | ||
| 235 | // strobe the beginnings of DRAM cycles |
240 | // strobe the beginnings of DRAM cycles |
| 236 | 241 | ||
| 237 | always @(posedge fclk) |
242 | always @(posedge fclk) |
| 238 | if( zneg ) |
243 | if( zneg ) |
| 239 | r_mreq_n <= mreq_n | (~rfsh_n); |
244 | r_mreq_n <= mreq_n | (~rfsh_n); |
| 240 | // |
245 | // |
| 241 | assign dram_beg = ( (!cache_hit) || memwr ) && zneg && r_mreq_n && (!romnram) && (!mreq_n) && rfsh_n; |
246 | assign dram_beg = ( !cache_hit || memwr ) && zneg && r_mreq_n && (!romnram) && (!mreq_n) && rfsh_n; |
| 242 | 247 | ||
| 243 | // access type |
248 | // access type |
| 244 | assign opfetch = (~mreq_n) && (~m1_n); |
249 | assign opfetch = (~mreq_n) && (~m1_n); |
| 245 | assign memrd = (~mreq_n) && (~rd_n); |
250 | assign memrd = (~mreq_n) && (~rd_n); |
| 246 | assign memwr = (~mreq_n) && rd_n && rfsh_n && (!wrdisable); |
251 | assign memwr = (~mreq_n) && rd_n && rfsh_n && (!wrdisable); |
| Line 324... | Line 329... | ||
| 324 | assign cpu_wrbsel = za[0]; |
329 | assign cpu_wrbsel = za[0]; |
| 325 | assign cpu_addr[20:0] = { page[7:0], za[13:1] }; |
330 | assign cpu_addr[20:0] = { page[7:0], za[13:1] }; |
| 326 | assign cpu_wrdata = zd_in; |
331 | assign cpu_wrdata = zd_in; |
| 327 | // |
332 | // |
| 328 | always @* if( cpu_strobe ) // WARNING! ACHTUNG! LATCH!!! |
333 | always @* if( cpu_strobe ) // WARNING! ACHTUNG! LATCH!!! |
| - | 334 | if (m1_n) |
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| - | 335 | data_cached_word <= cpu_rddata; |
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| - | 336 | else |
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| 329 | rd_buf <= cpu_rddata; |
337 | code_cached_word <= cpu_rddata; |
| - | 338 | ||
| 330 | // |
339 | // |
| 331 | assign zd_out = cpu_wrbsel ? rd_buf[7:0] : rd_buf[15:8]; |
340 | assign zd_out = cpu_wrbsel ? selected_cache[7:0] : selected_cache[15:8]; |
| 332 | 341 | ||
| 333 | 342 | ||
| 334 | 343 | ||
| 335 | 344 | ||
| 336 | 345 | ||
| Line 343... | Line 352... | ||
| 343 | if( zpos ) |
352 | if( zpos ) |
| 344 | io_r <= io; |
353 | io_r <= io; |
| 345 | // |
354 | // |
| 346 | always @(posedge fclk, negedge rst_n) |
355 | always @(posedge fclk, negedge rst_n) |
| 347 | if( !rst_n ) |
356 | if( !rst_n ) |
| - | 357 | begin |
|
| 348 | cached_addr_valid <= 1'b0; |
358 | code_cached_addr_valid <= 1'b0; |
| - | 359 | data_cached_addr_valid <= 1'b0; |
|
| - | 360 | end |
|
| 349 | else |
361 | else |
| 350 | begin |
362 | begin |
| 351 | if( (zneg && r_mreq_n && (!mreq_n) && rfsh_n && romnram) || |
363 | if( (zneg && r_mreq_n && (!mreq_n) && rfsh_n && romnram) || |
| 352 | (zneg && r_mreq_n && memwr ) || |
364 | (zneg && r_mreq_n && memwr ) || |
| 353 | (io && (!io_r) && zpos ) || |
365 | (io && (!io_r) && zpos ) || |
| 354 | (nmi_buf_clr ) ) |
366 | (nmi_buf_clr ) ) |
| - | 367 | begin |
|
| - | 368 | if (memwr) |
|
| - | 369 | begin |
|
| - | 370 | if (code_cache_select) |
|
| - | 371 | code_cached_addr_valid <= 1'b0; |
|
| - | 372 | if (data_cache_select) |
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| - | 373 | data_cached_addr_valid <= 1'b0; |
|
| - | 374 | end |
|
| - | 375 | else |
|
| - | 376 | begin |
|
| - | 377 | data_cached_addr_valid <= 1'b0; |
|
| 355 | cached_addr_valid <= 1'b0; |
378 | code_cached_addr_valid <= 1'b0; |
| - | 379 | end |
|
| - | 380 | end |
|
| 356 | else if( cpu_strobe ) |
381 | else if( cpu_strobe ) |
| - | 382 | begin |
|
| - | 383 | if (m1_n) |
|
| 357 | cached_addr_valid <= 1'b1; |
384 | data_cached_addr_valid <= 1'b1; |
| - | 385 | else |
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| - | 386 | code_cached_addr_valid <= 1'b1; |
|
| - | 387 | end |
|
| 358 | end |
388 | end |
| 359 | // |
389 | // |
| 360 | always @(posedge fclk) |
390 | always @(posedge fclk) |
| 361 | if( !rst_n ) |
391 | if( !rst_n ) |
| 362 | begin |
392 | begin |
| - | 393 | //code_cached_addr <= 15'd0; |
|
| 363 | cached_addr <= 15'd0; |
394 | //data_cached_addr <= 15'd0; |
| 364 | end |
395 | end |
| 365 | else if( cpu_strobe ) |
396 | else if( cpu_strobe ) |
| 366 | begin |
397 | begin |
| - | 398 | if (m1_n) |
|
| 367 | cached_addr[15:1] <= za[15:1]; |
399 | data_cached_addr[15:1] <= za[15:1]; |
| - | 400 | else |
|
| - | 401 | code_cached_addr[15:1] <= za[15:1]; |
|
| 368 | end |
402 | end |
| 369 | 403 | ||
| 370 | 404 | ||
| 371 | 405 | ||
| 372 | 406 | ||