Rev 97 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
Rev 97 | Rev 98 | ||
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Line 12... | Line 12... | ||
12 | 12 | ||
13 | input wire wr_stb, // write strobe: writes data from wd to the current wptr, increments wptr |
13 | input wire wr_stb, // write strobe: writes data from wd to the current wptr, increments wptr |
14 | input wire rd_stb, // read strobe: increments rptr |
14 | input wire rd_stb, // read strobe: increments rptr |
15 | 15 | ||
16 | output wire wdone, // write done - all 512 bytes are written (end of write operation) |
16 | output wire wdone, // write done - all 512 bytes are written (end of write operation) |
- | 17 | output wire w511, // write almost done -- at address 511 |
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17 | output wire rdone, // read done - all 512 bytes are read (end of read operation) |
18 | output wire rdone, // read done - all 512 bytes are read (end of read operation) |
18 | output wire empty, // fifo empty: when wptr==rptr (rd_stb must not be issued when empty is active, otherwise everytrhing desyncs) |
19 | output wire empty, // fifo empty: when wptr==rptr (rd_stb must not be issued when empty is active, otherwise everytrhing desyncs) |
19 | 20 | ||
20 | input wire [7:0] wd, // data to be written |
21 | input wire [7:0] wd, // data to be written |
21 | output wire [7:0] rd // data just read from rptr address |
22 | output wire [7:0] rd // data just read from rptr address |
Line 28... | Line 29... | ||
28 | if( !rst_n ) |
29 | if( !rst_n ) |
29 | wptr = 10'd0; |
30 | wptr = 10'd0; |
30 | else if( wr_stb ) |
31 | else if( wr_stb ) |
31 | wptr <= wptr + 10'd1; |
32 | wptr <= wptr + 10'd1; |
32 | 33 | ||
- | 34 | assign w511 = &wptr[8:0]; |
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- | 35 | ||
33 | always @(posedge clk, negedge rst_n) |
36 | always @(posedge clk, negedge rst_n) |
34 | if( !rst_n ) |
37 | if( !rst_n ) |
35 | rptr = 10'd0; |
38 | rptr = 10'd0; |
36 | else if( rd_stb ) |
39 | else if( rd_stb ) |
37 | rptr <= rptr + 10'd1; |
40 | rptr <= rptr + 10'd1; |
Line 40... | Line 43... | ||
40 | assign rdone = rptr[9]; |
43 | assign rdone = rptr[9]; |
41 | assign empty = ( wptr==rptr ); |
44 | assign empty = ( wptr==rptr ); |
42 | 45 | ||
43 | 46 | ||
44 | 47 | ||
45 | mem512b fifo512_oneshot_mem512b( .clk(clk), |
48 | mem512b fifo512_oneshot_mem512b |
- | 49 | ( |
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- | 50 | .clk(clk), |
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46 | 51 | ||
47 | .rdaddr(rptr[8:0]), |
52 | .rdaddr(rptr[8:0]), |
48 | .dataout(rd), |
53 | .dataout(rd), |
- | 54 | .re(rd_stb), |
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49 | 55 | ||
50 | .wraddr(wptr[8:0]), |
56 | .wraddr(wptr[8:0]), |
51 | .datain(wd), |
57 | .datain(wd), |
52 | .we(wr_stb) |
58 | .we(wr_stb) |
53 | ); |
59 | ); |
- | 60 | ||
- | 61 | ||
54 | endmodule |
62 | endmodule |
55 | 63 |