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1 | `include "../include/tune.v" |
1 | `include "../include/tune.v" |
2 | 2 | ||
3 | // PentEvo project (c) NedoPC 2008-2009 |
3 | // PentEvo project (c) NedoPC 2008-2011 |
4 | // |
4 | // |
5 | // DRAM arbiter. Shares DRAM between processor and video data fetcher |
5 | // DRAM arbiter. Shares DRAM between processor and video data fetcher |
6 | // |
6 | // |
- | 7 | ||
- | 8 | ||
- | 9 | ||
- | 10 | ||
- | 11 | ||
- | 12 | // 14.06.2011: |
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- | 13 | // removed cpu_stall and cpu_waitcyc. |
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- | 14 | // changed cpu_strobe behavior (only strobes read data arrival now). |
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- | 15 | // added cpu_next signal (shows whether next DRAM cycle CAN be grabbed by CPU) |
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- | 16 | // |
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- | 17 | // Now it is a REQUIREMENT for 'go' signal only starting and ending on |
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- | 18 | // beginning of DRAM cycle (i.e. right after 'cend' strobe). |
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- | 19 | // |
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- | 20 | ||
- | 21 | ||
- | 22 | // 13.06.2011: |
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- | 23 | // ╧Ёшф╕Єё яюЄЁхсютрЄ№, ўЄюс go єёЄрэртыштрыё ёЁрчє яюёых cend (є ьхэ [lvd] ¤Єю Єръ). |
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- | 24 | // ¤Єю фы Єюую, ўЄюс√ яЁюЎхёёюЁ эр 14ьуЎ ьюу чрЁрэхх ш т ы■сющ ьюьхэЄ чэрЄ№, эр |
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- | 25 | // ёъюы№ъю чртхщЄшЄ№ё . ┬ьхёЄю cpu_ack ттхфхь фЁєующ ёшуэры, ъюЄюЁ√щ т Єхўхэшх тёхую |
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- | 26 | // фЁрь-Ўшъыр сєфхЄ яюърч√трЄ№, ўхщ ьюцхЄ с√Є№ ёыхфє■∙шщ Ўшъы - яЁюЎхёёюЁр шыш Єюы№ъю |
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- | 27 | // тшфхю. ╧ю ёєЄш ¤Єю ш сєфхЄ Єръцх cpu_ack, эю трышфэ√щ т ьюьхэЄ cpu_req (Є.х. |
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- | 28 | // т ьюьхэЄ cend) ш Ёрэхх. |
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- | 29 | ||
- | 30 | // 12.06.2011: |
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- | 31 | // яЁюсыхьр: хёыш Ўяє яЁюёшЄ Ўшъы ўЄхэш , р хую фрЄ№ эх ьюуєЄ, |
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- | 32 | // Єю юэ фюыцхэ фхЁцрЄ№ cpu_req. юфэръю, ёэ Є№ юэ хую ьюцхЄ |
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- | 33 | // Єюы№ъю яю cpu_strobe, яЁш ¤Єюь Єръцх юЄяЁртшЄё х∙х юфшэ |
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- | 34 | // чряЁюё ўЄхэш !!! |
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- | 35 | // Ёх°хэшх: фюсртшЄ№ ёшуэры cpu_ack, яю ъюЄюЁюьє єчэр╕Єё , ўЄю |
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- | 36 | // рЁсшЄЁ чюїртры чряЁюё (чряшёш шыш ўЄхэш ), ъюЄюЁ√щ сєфхЄ |
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- | 37 | // ёютярфрЄ№ ё э√эх°эшь cpu_strobe эр чряшёш (cbeg), р сєфє∙шщ |
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- | 38 | // cpu_strobe ёфхырЄ№ Єюы№ъю ъръ ёЄЁюс фрээ√ї эр чюїртрээюь |
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- | 39 | // чряЁюёх ўЄхэ . |
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- | 40 | // ¤Єю, тючьюцэю, яючтюышЄ єфрышЄ№ тё ъшх cpu_waitcyc... |
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- | 41 | ||
- | 42 | ||
7 | // Arbitration is made on full 8-cycle access blocks. Each cycle is defined by dram.v and consists of 4 fpga clocks. |
43 | // Arbitration is made on full 8-cycle access blocks. Each cycle is defined by dram.v and consists of 4 fpga clocks. |
8 | // During each access block, there can be either no videodata access, 1 videodata access, 2, 4 or full 8 accesses. |
44 | // During each access block, there can be either no videodata access, 1 videodata access, 2, 4 or full 8 accesses. |
9 | // All spare cycles can be used by processor. If nobody uses memory in the given cycle, refresh cycle is performed |
45 | // All spare cycles can be used by processor. If nobody uses memory in the given cycle, refresh cycle is performed |
10 | // |
46 | // |
11 | // In each access block, videodata accesses are spreaded all over the block so that processor receives cycle |
47 | // In each access block, videodata accesses are spreaded all over the block so that processor receives cycle |
Line 72... | Line 108... | ||
72 | // if there is video_strobe, it coincides with cend signal |
108 | // if there is video_strobe, it coincides with cend signal |
73 | output reg video_next, // on this signal you can change video_addr; it is one clock leading the video_strobe |
109 | output reg video_next, // on this signal you can change video_addr; it is one clock leading the video_strobe |
74 | 110 | ||
75 | 111 | ||
76 | 112 | ||
- | 113 | input wire cpu_req, |
|
77 | input cpu_req,cpu_rnw, |
114 | input wire cpu_rnw, |
78 | input [20:0] cpu_addr, |
115 | input wire [20:0] cpu_addr, |
79 | input [7:0] cpu_wrdata, |
116 | input wire [ 7:0] cpu_wrdata, |
80 | input cpu_wrbsel, |
117 | input wire cpu_wrbsel, |
81 | 118 | ||
82 | output [15:0] cpu_rddata, |
119 | output wire [15:0] cpu_rddata, |
83 | output reg cpu_stall, |
120 | output reg cpu_next, |
84 | output [4:0] cpu_waitcyc, |
- | |
85 | output reg cpu_strobe |
121 | output reg cpu_strobe |
86 | ); |
122 | ); |
87 | 123 | ||
88 | wire cbeg; |
124 | wire cbeg; |
89 | 125 | ||
90 | reg [1:0] cctr; // DRAM cycle counter: 0 when cbeg is 1, then 1,2,3,0, etc... |
126 | reg [1:0] cctr; // DRAM cycle counter: 0 when cbeg is 1, then 1,2,3,0, etc... |
91 | 127 | ||
92 | 128 | ||
- | 129 | reg stall; |
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- | 130 | reg cpu_rnw_r; |
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93 | 131 | ||
94 | reg [2:0] blk_rem; // remaining accesses in a block (7..0) |
132 | reg [2:0] blk_rem; // remaining accesses in a block (7..0) |
95 | reg [2:0] blk_nrem; // remaining for the next dram cycle |
133 | reg [2:0] blk_nrem; // remaining for the next dram cycle |
96 | 134 | ||
97 | reg [2:0] vid_rem; // remaining video accesses in block (4..0) |
135 | reg [2:0] vid_rem; // remaining video accesses in block (4..0) |
Line 110... | Line 148... | ||
110 | reg [1:0] next_cycle; // type of the next cycle |
148 | reg [1:0] next_cycle; // type of the next cycle |
111 | 149 | ||
112 | 150 | ||
113 | 151 | ||
114 | 152 | ||
115 | reg [4:0] wait_new,wait_cyc; // how many cycles to wait until end of CPU cycle: _new is for next _cyc |
- | |
116 | reg [4:0] rw_add,vcyc_add; |
- | |
117 | - | ||
118 | - | ||
119 | 153 | ||
120 | initial // simulation only! |
154 | initial // simulation only! |
121 | begin |
155 | begin |
122 | curr_cycle = CYC_FREE; |
156 | curr_cycle = CYC_FREE; |
123 | blk_rem = 0; |
157 | blk_rem = 0; |
124 | vid_rem = 0; |
158 | vid_rem = 0; |
125 | cpu_stall = 0; |
- | |
126 | end |
159 | end |
127 | 160 | ||
128 | 161 | ||
129 | 162 | ||
130 | 163 | ||
Line 143... | Line 176... | ||
143 | always @(posedge clk) if( cend ) |
176 | always @(posedge clk) if( cend ) |
144 | begin |
177 | begin |
145 | blk_rem <= blk_nrem; |
178 | blk_rem <= blk_nrem; |
146 | 179 | ||
147 | if( (blk_rem==3'd0) ) |
180 | if( (blk_rem==3'd0) ) |
148 | cpu_stall <= (bw==2'd3) & go; |
181 | stall <= (bw==2'd3) & go; |
149 | end |
182 | end |
150 | 183 | ||
151 | always @* |
184 | always @* |
152 | begin |
185 | begin |
153 | if( (blk_rem==3'd0) && go ) |
186 | if( (blk_rem==3'd0) && go ) |
Line 186... | Line 219... | ||
186 | if( blk_rem==3'd0 ) |
219 | if( blk_rem==3'd0 ) |
187 | begin |
220 | begin |
188 | if( go ) |
221 | if( go ) |
189 | begin |
222 | begin |
190 | if( bw==2'b11 ) |
223 | if( bw==2'b11 ) |
- | 224 | begin |
|
- | 225 | cpu_next = 1'b0; |
|
- | 226 | ||
191 | next_cycle = CYC_VIDEO; |
227 | next_cycle = CYC_VIDEO; |
- | 228 | end |
|
192 | else |
229 | else |
- | 230 | begin |
|
- | 231 | cpu_next = 1'b1; |
|
- | 232 | ||
193 | if( cpu_req ) |
233 | if( cpu_req ) |
194 | next_cycle = CYC_CPU; |
234 | next_cycle = CYC_CPU; |
195 | else |
235 | else |
196 | next_cycle = CYC_VIDEO; |
236 | next_cycle = CYC_VIDEO; |
197 | end |
237 | end |
- | 238 | end |
|
198 | else // !go |
239 | else // !go |
199 | begin |
240 | begin |
- | 241 | cpu_next = 1'b1; |
|
- | 242 | ||
200 | if( cpu_req ) |
243 | if( cpu_req ) |
201 | next_cycle = CYC_CPU; |
244 | next_cycle = CYC_CPU; |
202 | else |
245 | else |
203 | next_cycle = CYC_FREE; |
246 | next_cycle = CYC_FREE; |
204 | end |
247 | end |
205 | end |
248 | end |
206 | else // blk_rem!=3'd0 |
249 | else // blk_rem!=3'd0 |
207 | begin |
250 | begin |
208 | if( cpu_stall ) |
251 | if( stall ) |
- | 252 | begin |
|
- | 253 | cpu_next = 1'b0; |
|
- | 254 | ||
209 | next_cycle = CYC_VIDEO; |
255 | next_cycle = CYC_VIDEO; |
- | 256 | end |
|
210 | else |
257 | else |
211 | begin |
258 | begin |
212 | if( vid_rem==blk_rem ) |
259 | if( vid_rem==blk_rem ) |
- | 260 | begin |
|
- | 261 | cpu_next = 1'b0; |
|
- | 262 | ||
213 | next_cycle = CYC_VIDEO; |
263 | next_cycle = CYC_VIDEO; |
- | 264 | end |
|
214 | else |
265 | else |
- | 266 | begin |
|
- | 267 | cpu_next = 1'b1; |
|
- | 268 | ||
215 | if( cpu_req ) |
269 | if( cpu_req ) |
216 | next_cycle = CYC_CPU; |
270 | next_cycle = CYC_CPU; |
217 | else |
271 | else |
218 | if( vid_rem==3'd0 ) |
272 | if( vid_rem==3'd0 ) |
219 | next_cycle = CYC_FREE; |
273 | next_cycle = CYC_FREE; |
220 | else |
274 | else |
221 | next_cycle = CYC_VIDEO; |
275 | next_cycle = CYC_VIDEO; |
222 | end |
276 | end |
223 | end |
277 | end |
224 | end |
278 | end |
- | 279 | end |
|
- | 280 | ||
225 | 281 | ||
226 | 282 | ||
227 | 283 | ||
228 | // just current cycle register |
284 | // just current cycle register |
229 | always @(posedge clk) if( cend ) |
285 | always @(posedge clk) if( cend ) |
Line 261... | Line 317... | ||
261 | end |
317 | end |
262 | end |
318 | end |
263 | 319 | ||
264 | 320 | ||
265 | 321 | ||
266 | // generation of strobes: for video and cpu |
322 | // generation of read strobes: for video and cpu |
- | 323 | ||
- | 324 | ||
- | 325 | always @(posedge clk) |
|
- | 326 | if( cend ) |
|
267 | // for cpu, write strobe is earlier than read one |
327 | cpu_rnw_r <= cpu_rnw; |
268 | 328 | ||
269 | 329 | ||
270 | always @(posedge clk) |
330 | always @(posedge clk) |
271 | begin |
331 | begin |
272 | if( (next_cycle==CYC_CPU) && cend && (!cpu_rnw) ) |
- | |
273 | cpu_strobe <= 1'b1; |
- | |
274 | else if( (curr_cycle==CYC_CPU) && cpu_rnw && pre_cend ) |
332 | if( (curr_cycle==CYC_CPU) && cpu_rnw_r && pre_cend ) |
275 | cpu_strobe <= 1'b1; |
333 | cpu_strobe <= 1'b1; |
276 | else |
334 | else |
277 | cpu_strobe <= 1'b0; |
335 | cpu_strobe <= 1'b0; |
- | 336 | end |
|
278 | 337 | ||
279 | 338 | ||
- | 339 | always @(posedge clk) |
|
- | 340 | begin |
|
280 | if( (curr_cycle==CYC_VIDEO) && pre_cend ) |
341 | if( (curr_cycle==CYC_VIDEO) && pre_cend ) |
281 | video_strobe <= 1'b1; |
342 | video_strobe <= 1'b1; |
282 | else |
343 | else |
283 | video_strobe <= 1'b0; |
344 | video_strobe <= 1'b0; |
284 | 345 | ||
Line 288... | Line 349... | ||
288 | video_next <= 1'b0; |
349 | video_next <= 1'b0; |
289 | end |
350 | end |
290 | 351 | ||
291 | 352 | ||
292 | 353 | ||
293 | // generate cpu_waitcyc |
- | |
294 | - | ||
295 | always @* |
- | |
296 | begin |
- | |
297 | rw_add = cpu_rnw ? 5'd3 : 5'd0; |
- | |
298 | - | ||
299 | if( (vid_rem==blk_rem) && (!cpu_stall) ) |
- | |
300 | vcyc_add[4:0] = {blk_rem[2:0],2'b00}; |
- | |
301 | else |
- | |
302 | vcyc_add[4:0] = 5'd0; |
- | |
303 | - | ||
304 | wait_new = rw_add + vcyc_add; |
- | |
305 | end |
- | |
306 | - | ||
307 | - | ||
308 | always @(posedge clk) |
- | |
309 | begin |
- | |
310 | if( (wait_cyc!=5'd0) ) |
- | |
311 | begin |
- | |
312 | if( !cpu_stall ) |
- | |
313 | wait_cyc <= wait_cyc - 5'd1; |
- | |
314 | end |
- | |
315 | else // wait_cyc==0 |
- | |
316 | begin |
- | |
317 | if( cend && cpu_req ) |
- | |
318 | begin |
- | |
319 | wait_cyc <= wait_new; |
- | |
320 | end |
- | |
321 | end |
- | |
322 | - | ||
323 | - | ||
324 | end |
- | |
325 | - | ||
326 | - | ||
327 | assign cpu_waitcyc = wait_cyc; |
- | |
328 | - | ||
329 | - | ||
330 | - | ||
331 | endmodule |
354 | endmodule |
332 | 355 |