Rev 425 | Show entire file | Regard whitespace | Details | Blame | Last modification | View Log | RSS feed
| Rev 425 | Rev 668 | ||
|---|---|---|---|
| Line 1... | Line -... | ||
| 1 | `include "../include/tune.v" |
- | |
| 2 | - | ||
| 3 | // PentEvo project (c) NedoPC 2008-2009 |
1 | // ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014 |
| 4 | // |
2 | // |
| 5 | // DRAM controller. performs accesses to DRAM. |
3 | // DRAM controller. performs accesses to DRAM. |
| - | 4 | ||
| - | 5 | /* |
|
| - | 6 | This file is part of ZX-Evo Base Configuration firmware. |
|
| - | 7 | ||
| - | 8 | ZX-Evo Base Configuration firmware is free software: |
|
| - | 9 | you can redistribute it and/or modify it under the terms of |
|
| - | 10 | the GNU General Public License as published by |
|
| - | 11 | the Free Software Foundation, either version 3 of the License, or |
|
| - | 12 | (at your option) any later version. |
|
| - | 13 | ||
| - | 14 | ZX-Evo Base Configuration firmware is distributed in the hope that |
|
| - | 15 | it will be useful, but WITHOUT ANY WARRANTY; without even |
|
| - | 16 | the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. |
|
| - | 17 | See the GNU General Public License for more details. |
|
| - | 18 | ||
| - | 19 | You should have received a copy of the GNU General Public License |
|
| - | 20 | along with ZX-Evo Base Configuration firmware. |
|
| - | 21 | If not, see <http://www.gnu.org/licenses/>. |
|
| - | 22 | */ |
|
| - | 23 | ||
| - | 24 | ||
| - | 25 | // |
|
| 6 | // |
26 | // |
| 7 | // state: | RD1 | RD2 | RD3 | RD4 | WR1 | WR2 | WR3 | WR4 | RFSH1 | RFSH2 | RFSH3 | RFSH4 | |
27 | // state: | RD1 | RD2 | RD3 | RD4 | WR1 | WR2 | WR3 | WR4 | RFSH1 | RFSH2 | RFSH3 | RFSH4 | |
| 8 | // clk: ___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\__ |
28 | // clk: ___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\___/```\__ |
| 9 | // | READ CYCLE | WRITE CYCLE | REFRESH CYCLE | |
29 | // | READ CYCLE | WRITE CYCLE | REFRESH CYCLE | |
| 10 | // ras: ```````````````````\_______________/```````````````\_______________/```````````````````````\_______________/ |
30 | // ras: ```````````````````\_______________/```````````````\_______________/```````````````````````\_______________/ |
| Line 25... | Line 45... | ||
| 25 | // ra[] couldn't be such in acex1k, because output registers could be all driven only by |
45 | // ra[] couldn't be such in acex1k, because output registers could be all driven only by |
| 26 | // single clock polarity (and here they are driven by negative edge, while CAS/RAS by positive) |
46 | // single clock polarity (and here they are driven by negative edge, while CAS/RAS by positive) |
| 27 | // |
47 | // |
| 28 | // rst_n is resynced before use and acts as req inhibit. so while in reset, dram regenerates and isn't corrupted |
48 | // rst_n is resynced before use and acts as req inhibit. so while in reset, dram regenerates and isn't corrupted |
| 29 | 49 | ||
| - | 50 | `include "../include/tune.v" |
|
| - | 51 | ||
| 30 | module dram( |
52 | module dram( |
| 31 | 53 | ||
| 32 | input clk, |
54 | input clk, |
| 33 | input rst_n, // shut down accesses, remain refresh |
55 | input rst_n, // shut down accesses, remain refresh |
| 34 | 56 | ||