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        begin
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        begin
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                state = RFSH1; // for simulation only!
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                state = RFSH1; // for simulation only!
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                rfsh_alt = 1'b0;
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                rfsh_alt = 1'b0;
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        end
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        end
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/*
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`ifdef SIMULATE
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`ifdef SIMULATE
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        always @(posedge clk)
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        always @(posedge clk)
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        begin
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        begin
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                if( req && !rnw && (state==RD4 || state==WR4 || state==RFSH4) )
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                if( req && !rnw && (state==RD4 || state==WR4 || state==RFSH4) )
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                begin
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                begin
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                        $display("written word %x mask %x to address %x",wrdata&{ {8{bsel[1]}}, {8{bsel[0]}} },{ {8{bsel[1]}}, {8{bsel[0]}} },addr);
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                        $display("written word %x mask %x to address %x",wrdata&{ {8{bsel[1]}}, {8{bsel[0]}} },{ {8{bsel[1]}}, {8{bsel[0]}} },addr);
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                end
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                end
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        end
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        end
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`endif
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`endif
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*/
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        always @(posedge clk)
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        always @(posedge clk)
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        begin
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        begin
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                state <= next_state;
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                state <= next_state;
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        end
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        end