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        reg [2:0] req;
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        reg [2:0] req;
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        reg [2:0] pri_req;
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        reg [2:0] pri_req;
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        wire [2:0] enareq;
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        // M1 signal beginning
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        // M1 signal beginning
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        always @(posedge clk)
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        always @(posedge clk)
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                {m1_rr, m1_r} <= {m1_r, m1_n};
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                {m1_rr, m1_r} <= {m1_r, m1_n};
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        // readback requests
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        // readback requests
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        assign req_rd = { 5'd0, req[2:0] };
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        assign req_rd = { 5'd0, req[2:0] };
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        assign enareq = req & ena;
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        // make prioritized request position
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        // make prioritized request position
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        always @(posedge clk)
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        always @(posedge clk)
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        if( m1_beg )
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        if( m1_beg )
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        begin
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        begin
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                pri_req[0] <=  req[0] ;
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                pri_req[0] <=  enareq[0] ;
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                pri_req[1] <= !req[0] &&  req[1] ;
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                pri_req[1] <= !enareq[0] &&  enareq[1] ;
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                pri_req[2] <= !req[0] && !req[1] && req[2];
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                pri_req[2] <= !enareq[0] && !enareq[1] && enareq[2];
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        end
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        end
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        //
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        //
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        assign int_vector = { 1'b1, ~pri_req[2], ~pri_req[1] }; // for 3 requests only
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        assign int_vector = { 1'b1, ~pri_req[2], ~pri_req[1] }; // for 3 requests only
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        // gen interrupt
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        // gen interrupt
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        always @(posedge clk)
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        always @(posedge clk)
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                int_n <= !( req & ena );
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                int_n <= !enareq;
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endmodule
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endmodule
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