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set_global_assignment -name TOP_LEVEL_ENTITY top
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set_global_assignment -name TOP_LEVEL_ENTITY top
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:27  OCTOBER 13, 2012"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:32:27  OCTOBER 13, 2012"
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set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
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set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
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set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE AREA
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set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE BALANCED
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set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
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set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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set_global_assignment -name DEVICE_FILTER_PIN_COUNT 100
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
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set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
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set_global_assignment -name VERILOG_FILE ../rtl/ports.v
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set_global_assignment -name VERILOG_FILE ../rtl/ports.v
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set_global_assignment -name VERILOG_FILE ../rtl/top.v
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set_global_assignment -name VERILOG_FILE ../rtl/top.v