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| Rev 132 | Rev 133 | ||
|---|---|---|---|
| Line 127... | Line 127... | ||
| 127 | wr_state <= 1'b0; |
127 | wr_state <= 1'b0; |
| 128 | rd_state <= 1'b0; |
128 | rd_state <= 1'b0; |
| 129 | end |
129 | end |
| 130 | else |
130 | else |
| 131 | begin |
131 | begin |
| 132 | if( wr_regs[2:1]==2'b01 && !wr_state ) |
132 | if( wr_regs[1:0]==2'b01 && !wr_state ) |
| 133 | wr_state <= 1'b1; |
133 | wr_state <= 1'b1; |
| 134 | else if( wr_regs[2:1]==2'b00 && wr_state ) |
134 | else if( wr_regs[1:0]==2'b00 && wr_state ) |
| 135 | wr_state <= 1'b0; |
135 | wr_state <= 1'b0; |
| 136 | // |
136 | // |
| 137 | if( rd_regs[2:1]==2'b01 && !rd_state ) |
137 | if( rd_regs[1:0]==2'b01 && !rd_state ) |
| 138 | rd_state <= 1'b1; |
138 | rd_state <= 1'b1; |
| 139 | else if( rd_regs[2:1]==2'b00 && rd_state ) |
139 | else if( rd_regs[1:0]==2'b00 && rd_state ) |
| 140 | rd_state <= 1'b0; |
140 | rd_state <= 1'b0; |
| 141 | end |
141 | end |
| 142 | // |
142 | // |
| 143 | assign wr_start = wr_regs[2:1]==2'b01 && !wr_state; |
143 | assign wr_start = wr_regs[1:0]==2'b01 && !wr_state; |
| 144 | assign rd_start = rd_regs[2:1]==2'b01 && !rd_state; |
144 | assign rd_start = rd_regs[1:0]==2'b01 && !rd_state; |
| 145 | 145 | ||
| 146 | 146 | ||
| 147 | // buffered rd/wrs |
147 | // buffered rd/wrs |
| 148 | always @(posedge fclk) |
148 | always @(posedge fclk) |
| 149 | begin |
149 | begin |
| Line 177... | Line 177... | ||
| 177 | end |
177 | end |
| 178 | // |
178 | // |
| 179 | always @(posedge fclk) |
179 | always @(posedge fclk) |
| 180 | if( wr_start || rd_start ) |
180 | if( wr_start || rd_start ) |
| 181 | begin |
181 | begin |
| 182 | w5300_cs_n <= r_w5300_cs_n[0]; |
182 | w5300_cs_n <= async_w5300_cs_n; |
| 183 | sl811_cs_n <= r_sl811_cs_n[0]; |
183 | sl811_cs_n <= async_sl811_cs_n; |
| 184 | end |
184 | end |
| 185 | else if( !ctr_5 ) |
185 | else if( !ctr_5 ) |
| 186 | begin |
186 | begin |
| 187 | w5300_cs_n <= 1'b1; |
187 | w5300_cs_n <= 1'b1; |
| 188 | sl811_cs_n <= 1'b1; |
188 | sl811_cs_n <= 1'b1; |
| Line 193... | Line 193... | ||
| 193 | always @(posedge fclk) |
193 | always @(posedge fclk) |
| 194 | r_sl811_a0[1:0] <= { r_sl811_a0[0], async_sl811_a0 }; |
194 | r_sl811_a0[1:0] <= { r_sl811_a0[0], async_sl811_a0 }; |
| 195 | // |
195 | // |
| 196 | always @(posedge fclk) |
196 | always @(posedge fclk) |
| 197 | if( wr_start || rd_start ) |
197 | if( wr_start || rd_start ) |
| 198 | sl811_a0 <= r_sl811_a0[0]; |
198 | sl811_a0 <= async_sl811_a0; |
| 199 | 199 | ||
| 200 | 200 | ||
| 201 | 201 | ||
| 202 | // buffered w5300_addr |
202 | // buffered w5300_addr |
| 203 | always @(posedge fclk) |
203 | always @(posedge fclk) |
| Line 206... | Line 206... | ||
| 206 | r_w5300_addr[1] <= r_w5300_addr[0]; |
206 | r_w5300_addr[1] <= r_w5300_addr[0]; |
| 207 | end |
207 | end |
| 208 | // |
208 | // |
| 209 | always @(posedge fclk) |
209 | always @(posedge fclk) |
| 210 | if( wr_start || rd_start ) |
210 | if( wr_start || rd_start ) |
| 211 | w5300_addr <= r_w5300_addr[0]; |
211 | w5300_addr <= async_w5300_addr; |
| 212 | 212 | ||
| 213 | 213 | ||
| 214 | 214 | ||
| 215 | 215 | ||
| 216 | 216 | ||