Subversion Repositories pentevo

# Copyright (C) 1991-2007 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#               top_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#               assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY MAX3000A
set_global_assignment -name DEVICE "EPM3032ATC44-10"
set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "7.2 SP3"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "01:33:26  AUGUST 08, 2025"
set_global_assignment -name LAST_QUARTUS_VERSION "7.2 SP3"
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
set_global_assignment -name EDA_INCLUDE_VHDL_CONFIGURATION_DECLARATION ON -section_id eda_simulation
set_global_assignment -name EDA_NETLIST_WRITER_OUTPUT_DIR sim/gate -section_id eda_simulation
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 44
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 10
set_global_assignment -name VERILOG_FILE ../rtl/top.v

set_location_assignment PIN_37 -to fclk
set_location_assignment PIN_44 -to fclk_fpga
set_location_assignment PIN_43 -to fclk_vdac

set_location_assignment PIN_2  -to v_r[1]
set_location_assignment PIN_3  -to v_r[0]
set_location_assignment PIN_5  -to v_g[1]
set_location_assignment PIN_6  -to v_g[0]
set_location_assignment PIN_8  -to v_b[1]
set_location_assignment PIN_10 -to v_b[0]

set_location_assignment PIN_34 -to vvsync
set_location_assignment PIN_35 -to vhsync
set_location_assignment PIN_42 -to vcsync

set_location_assignment PIN_27 -to d_r[3]
set_location_assignment PIN_25 -to d_r[2]
set_location_assignment PIN_23 -to d_r[1]
set_location_assignment PIN_22 -to d_r[0]
set_location_assignment PIN_21 -to d_g[3]
set_location_assignment PIN_20 -to d_g[2]
set_location_assignment PIN_19 -to d_g[1]
set_location_assignment PIN_18 -to d_g[0]
set_location_assignment PIN_15 -to d_b[3]
set_location_assignment PIN_14 -to d_b[2]
set_location_assignment PIN_13 -to d_b[1]
set_location_assignment PIN_12 -to d_b[0]

set_location_assignment PIN_33 -to fl_vs
set_location_assignment PIN_31 -to fl_hs
set_location_assignment PIN_28 -to fl_cs