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  1. // part of NeoGS project
  2. //
  3. // (c) NedoPC 2007-2013
  4. //
  5. // this is dma "one-shot" fifo: after each 512 bytes both written and read back, it must be initialized by means of 'init'
  6. //
  7.  
  8. module dma_fifo_oneshot(
  9.  
  10.         input  wire clk,
  11.         input  wire rst_n,
  12.  
  13.         input  wire wr_stb, // write strobe: writes data from wd to the current wptr, increments wptr
  14.         input  wire rd_stb, // read strobe: increments rptr
  15.  
  16.         output wire wdone, // write done - all 512 bytes are written (end of write operation)
  17.         output wire rdone, // read done - all 512 bytes are read (end of read operation)
  18.         output wire empty, // fifo empty: when wptr==rptr (rd_stb must not be issued when empty is active, otherwise everytrhing desyncs)
  19.  
  20.         input  wire [7:0] wd, // data to be written
  21.         output wire [7:0] rd  // data just read from rptr address
  22. );
  23.  
  24.         reg [9:0] wptr;
  25.         reg [9:0] rptr;
  26.  
  27.         always @(posedge clk, negedge rst_n)
  28.         if( !rst_n )
  29.                 wptr = 10'd0;
  30.         else if( wr_stb )
  31.                 wptr <= wptr + 10'd1;
  32.        
  33.         always @(posedge clk, negedge rst_n)
  34.         if( !rst_n )
  35.                 rptr = 10'd0;
  36.         else if( rd_stb )
  37.                 rptr <= rptr + 10'd1;
  38.  
  39.         assign wdone = wptr[9];
  40.         assign rdone = rptr[9];
  41.         assign empty = ( wptr==rptr );
  42.  
  43.  
  44.  
  45.         mem512b fifo512_oneshot_mem512b( .clk(clk),
  46.  
  47.                                          .rdaddr(rptr[8:0]),
  48.                                          .dataout(rd),
  49.  
  50.                                          .wraddr(wptr[8:0]),
  51.                                          .datain(wd),
  52.                                          .we(wr_stb)
  53.                                        );
  54. endmodule
  55.  
  56.