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Project Information c:\final\p1024sl.rptMAX+plus II Compiler Report FileVersion 10.0 9/14/2000Compiled: 10/05/2007 19:59:35Copyright (C) 1988-2000 Altera CorporationAny megafunction design, and related net list (encrypted or decrypted),support information, device programming or simulation file, and any otherassociated documentation or information provided by Altera or a partnerunder Altera's Megafunction Partnership Program may be used only toprogram PLD devices (but not masked PLD devices) from Altera. Any otheruse of such megafunction design, net list, support information, deviceprogramming or simulation file, or any other related documentation orinformation is prohibited for any other purpose, including, but notlimited to modification, reverse engineering, de-compiling, or use withany other silicon devices, unless such use is explicitly licensed undera separate agreement with Altera or a megafunction partner. Title tothe intellectual property, including patents, copyrights, trademarks,trade secrets, or maskworks, embodied in any such megafunction design,net list, support information, device programming or simulation file, orany other related documentation or information provided by Altera or amegafunction partner, remains with Altera, the megafunction partner, ortheir respective licensors. No other licenses, including any licensesneeded under any third party's intellectual property, are provided herein.***** Project compilation was successfulP1024SL** DEVICE SUMMARY **Chip/ Input Output Bidir ShareablePOF Device Pins Pins Pins LCs Expanders % Utilizedp1024sl EPM7128SLC84-6 27 37 0 114 76 89 %User Pins: 27 37 0Project Information c:\final\p1024sl.rpt** PROJECT COMPILATION MESSAGES **Warning: GLOBAL primitive on node 'res' feeds logic -- non-global signal usage may resultProject Information c:\final\p1024sl.rpt** AUTO GLOBAL SIGNALS **INFO: Signal 'f14' chosen for auto global ClockINFO: Signal 'res' chosen for auto global ClearProject Information c:\final\p1024sl.rpt** PIN/LOCATION/CHIP ASSIGNMENTS **ActualUser AssignmentsAssignments (if different) Node Namep1024sl@57 av0p1024sl@12 av1p1024sl@17 av2p1024sl@18 av3p1024sl@22 av4p1024sl@73 av5p1024sl@77 av6p1024sl@56 av7p1024sl@76 av8p1024sl@75 av9p1024sl@74 av10p1024sl@81 av11p1024sl@80 av12p1024sl@58 av13p1024sl@54 av14p1024sl@5 av15p1024sl@4 a14p1024sl@6 a15p1024sl@44 bp1024sl@10 brightp1024sl@51 busrqp1024sl@50 casp1024sl@70 clkp1024sl@24 csosp1024sl@15 dosp1024sl@61 d0p1024sl@60 d1p1024sl@64 d2p1024sl@68 d3p1024sl@69 d4p1024sl@67 d5p1024sl@65 d6p1024sl@63 d7p1024sl@83 f14p1024sl@79 gp1024sl@48 hlp1024sl@11 intp1024sl@2 iorqp1024sl@30 mem0p1024sl@28 mem1p1024sl@27 mem2p1024sl@25 mem3p1024sl@20 mreqp1024sl@8 port1p1024sl@9 port2p1024sl@55 rp1024sl@33 ram0p1024sl@34 ram1p1024sl@35 ram2p1024sl@36 ram3p1024sl@37 ram4p1024sl@39 ram5p1024sl@40 ram6p1024sl@41 ram7p1024sl@49 rasp1024sl@84 rdp1024sl@1 resp1024sl@21 rfshp1024sl@52 syncp1024sl@29 waitp1024sl@46 wep1024sl@45 x2p1024sl@16 y0p1024sl@31 y1Device-Specific Information: c:\final\p1024sl.rptp1024sl***** Logic for device 'p1024sl' compiled without errors.Device: EPM7128SLC84-6Device Options:Turbo Bit = ONSecurity Bit = OFFEnable JTAG Support = ONUser Code = ffffMultiVolt I/O = OFFDevice-Specific Information: c:\final\p1024sl.rptp1024sl** ERROR SUMMARY **Info: Chip 'p1024sl' in device 'EPM7128SLC84-6' has less than 20% of pins available for future logic changes -- if your project is likely to change, Altera recommends using a larger deviceb Vr p p C Vi o o a C i a a Ci g r r G a v a I o r f G v v C a a an h t t N 1 1 1 N r e r 1 N 1 1 I v v vt t 2 1 D 5 5 4 T q s d 4 D 1 2 g O 6 8 9-----------------------------------------------------------------_/ 11 10 9 8 7 6 5 4 3 2 1 84 83 82 81 80 79 78 77 76 75 |av1 | 12 74 | av10VCCIO | 13 73 | av5#TDI | 14 72 | GNDdos | 15 71 | #TDOy0 | 16 70 | clkav2 | 17 69 | d4av3 | 18 68 | d3GND | 19 67 | d5mreq | 20 66 | VCCIOrfsh | 21 65 | d6av4 | 22 EPM7128SLC84-6 64 | d2#TMS | 23 63 | d7csos | 24 62 | #TCKmem3 | 25 61 | d0VCCIO | 26 60 | d1mem2 | 27 59 | GNDmem1 | 28 58 | av13wait | 29 57 | av0mem0 | 30 56 | av7y1 | 31 55 | rGND | 32 54 | av14|_ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 _|------------------------------------------------------------------r r r r r V r r r G V b x w G h r c b s Va a a a a C a a a N C 2 e N l a a u y Cm m m m m C m m m D C D s s s n C0 1 2 3 4 I 5 6 7 I r c IO N q OTN.C. = No Connect. This pin has no internal connection to the device.VCCINT = Dedicated power pin, which MUST be connected to VCC (5.0 volts).VCCIO = Dedicated power pin, which MUST be connected to VCC (5.0 volts).GND = Dedicated ground pin or unused dedicated input, which MUST be connected to GND.RESERVED = Unused I/O pin, which MUST be left unconnected.^ = Dedicated configuration pin.+ = Reserved configuration pin, which is tri-stated during user mode.* = Reserved configuration pin, which drives out in user mode.PDn = Power Down pin.@ = Special-purpose pin.# = JTAG Boundary-Scan Testing/In-System Programming or Configuration Pin. The JTAG inputs TMS and TDI should be tied to VCC and TCK should be tied to GND when not in use.& = JTAG pin used for I/O. When used as user I/O, JTAG pins must be kept stable before and during configuration. JTAG pin stability prevents accidental loading of JTAG instructions.Device-Specific Information: c:\final\p1024sl.rptp1024sl** RESOURCE USAGE **Shareable ExternalLogic Array Block Logic Cells I/O Pins Expanders InterconnectA: LC1 - LC16 15/16( 93%) 8/ 8(100%) 14/16( 87%) 31/36( 86%)B: LC17 - LC32 16/16(100%) 8/ 8(100%) 13/16( 81%) 30/36( 83%)C: LC33 - LC48 16/16(100%) 8/ 8(100%) 8/16( 50%) 29/36( 80%)D: LC49 - LC64 16/16(100%) 8/ 8(100%) 6/16( 37%) 16/36( 44%)E: LC65 - LC80 9/16( 56%) 8/ 8(100%) 14/16( 87%) 31/36( 86%)F: LC81 - LC96 14/16( 87%) 8/ 8(100%) 16/16(100%) 31/36( 86%)G: LC97 - LC112 12/16( 75%) 8/ 8(100%) 3/16( 18%) 28/36( 77%)H: LC113 - LC128 16/16(100%) 8/ 8(100%) 16/16(100%) 31/36( 86%)Total dedicated input pins used: 4/4 (100%)Total I/O pins used: 64/64 (100%)Total logic cells used: 114/128 ( 89%)Total shareable expanders used: 76/128 ( 59%)Total Turbo logic cells used: 114/128 ( 89%)Total shareable expanders not available (n/a): 14/128 ( 10%)Average fan-in: 6.02Total fan-in: 687Total input pins required: 27Total fast input logic cells required: 0Total output pins required: 37Total bidirectional pins required: 0Total reserved pins required 4Total logic cells required: 114Total flipflops required: 87Total product terms required: 378Total logic cells lending parallel expanders: 0Total shareable expanders in database: 45Synthesized logic cells: 10/ 128 ( 7%)Device-Specific Information: c:\final\p1024sl.rptp1024sl** INPUTS **ShareableExpanders Fan-In Fan-OutPin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name4 (16) (A) INPUT 0 0 0 0 0 8 1 a146 (13) (A) INPUT 0 0 0 0 0 8 1 a1515 (29) (B) INPUT 0 0 0 0 0 0 1 dos61 (94) (F) INPUT 0 0 0 0 0 0 3 d060 (93) (F) INPUT 0 0 0 0 0 0 2 d164 (99) (G) INPUT 0 0 0 0 0 0 3 d268 (105) (G) INPUT 0 0 0 0 0 1 1 d369 (107) (G) INPUT 0 0 0 0 0 1 1 d467 (104) (G) INPUT 0 0 0 0 0 0 1 d565 (101) (G) INPUT 0 0 0 0 0 0 2 d663 (97) (G) INPUT 0 0 0 0 0 0 1 d783 - - INPUT G 0 0 0 0 0 0 0 f142 - - INPUT 0 0 0 0 0 2 12 iorq20 (21) (B) INPUT 0 0 0 0 0 2 1 mreq8 (11) (A) INPUT 0 0 0 0 0 2 14 port19 (8) (A) INPUT 0 0 0 0 0 2 14 port233 (64) (D) INPUT 0 0 0 0 0 0 2 ram034 (61) (D) INPUT 0 0 0 0 0 0 2 ram135 (59) (D) INPUT 0 0 0 0 0 0 2 ram236 (57) (D) INPUT 0 0 0 0 0 0 2 ram337 (56) (D) INPUT 0 0 0 0 0 0 2 ram439 (53) (D) INPUT 0 0 0 0 0 0 2 ram540 (51) (D) INPUT 0 0 0 0 0 0 2 ram641 (49) (D) INPUT 0 0 0 0 0 0 2 ram784 - - INPUT 0 0 0 0 0 1 0 rd1 - - INPUT G 0 0 0 0 0 0 1 res21 (19) (B) INPUT 0 0 0 0 0 1 2 rfshCode:s = Synthesized pin or logic cellt = Turbo logic cell+ = Synchronous flipflop/ = Slow slew-rate output! = NOT gate push-backr = Fitter-inserted logic cellG = Global Source. Fan-out destinations counted here do not include destinationsthat are driven using global routing resources. Refer to the Auto Global Signals,Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear SignalsSections of this Report File for information on which signals' fan-outs are used asClock, Clear, Preset, Output Enable, and synchronous Load signals.Device-Specific Information: c:\final\p1024sl.rptp1024sl** OUTPUTS **ShareableExpanders Fan-In Fan-OutPin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name57 88 F FF t 0 0 0 0 3 4 2 av012 3 A FF t 0 0 0 0 4 3 1 av117 25 B FF t 8 8 0 0 8 5 2 av218 24 B FF t 8 8 0 0 8 5 3 av322 17 B FF t 8 8 0 0 8 7 2 av473 115 H FF t 0 0 0 0 3 1 0 av577 123 H FF t 0 0 0 0 4 7 9 av656 86 F FF t 0 0 0 0 5 7 9 av776 120 H OUTPUT t 0 0 0 0 4 0 0 av875 118 H OUTPUT t 0 0 0 0 4 0 0 av974 117 H OUTPUT t 0 0 0 0 3 0 0 av1081 128 H OUTPUT t 0 0 0 0 5 0 0 av1180 126 H OUTPUT t 0 0 0 0 3 0 0 av1258 91 F OUTPUT t 0 0 0 0 4 0 0 av1354 83 F OUTPUT t 0 0 0 0 6 0 0 av145 14 A FF t 1 1 0 4 3 0 0 av1544 65 E FF t 13 8 0 0 18 0 0 b10 6 A FF t 13 8 1 0 15 0 0 bright51 77 E OUTPUT t 0 0 0 0 6 0 0 busrq50 75 E FF + t ! 0 0 0 0 1 1 2 cas70 109 G FF + t 0 0 0 0 3 2 12 clk24 46 C FF t 1 1 0 4 3 0 0 csos79 125 H FF t 13 8 0 0 18 0 0 g48 72 E FF t 1 0 1 4 4 3 19 hl11 5 A FF t 0 0 0 0 6 0 0 int30 37 C OUTPUT t 0 0 0 2 2 0 0 mem028 40 C OUTPUT t 0 0 0 2 2 0 0 mem127 43 C OUTPUT t 0 0 0 2 2 0 0 mem225 45 C OUTPUT t 0 0 0 2 2 0 0 mem355 85 F FF t 13 8 0 0 18 0 0 r49 73 E FF + t ! 0 0 0 0 1 1 16 ras52 80 E OUTPUT t 0 0 0 0 7 0 0 sync29 38 C OUTPUT t 0 0 0 0 3 0 0 wait46 69 E OUTPUT t 0 0 0 4 2 0 0 we45 67 E FF t 0 0 0 0 1 6 11 x216 27 B OUTPUT t 0 0 0 2 1 0 0 y031 35 C OUTPUT t 0 0 0 2 1 0 0 y1Code:s = Synthesized pin or logic cellt = Turbo logic cell+ = Synchronous flipflop/ = Slow slew-rate output! = NOT gate push-backr = Fitter-inserted logic cellDevice-Specific Information: c:\final\p1024sl.rptp1024sl** BURIED LOGIC **ShareableExpanders Fan-In Fan-OutPin LC LAB Primitive Code Total Shared n/a INP FBK OUT FBK Name- 26 B DFFE t 0 0 0 0 6 4 9 bordtrg- 66 E TFFE t 0 0 0 0 3 3 2 countstr- 95 F TFFE t 0 0 0 0 2 6 18 count11(20) 21 B TFFE t 8 8 0 0 8 10 8 count23- 119 H TFFE t 0 0 0 0 1 3 1 count30- 124 H TFFE t 0 0 0 0 2 3 0 count31- 102 G TFFE t 0 0 0 0 5 11 17 count41(71) 112 G TFFE t 0 0 0 0 5 12 17 count42- 30 B TFFE t 1 0 1 0 5 8 8 count43- 42 C DFFE t 0 0 0 1 2 1 1 delay- 28 B SOFT s t 1 0 1 0 7 4 0 dsp~1(69) 107 G TFFE t 0 0 0 0 4 0 4 flash0(64) 99 G TFFE t 0 0 0 0 5 0 3 flash1- 116 H TFFE t 0 0 0 0 6 0 2 flash2- 127 H TFFE t 0 0 0 0 7 0 1 flash3- 113 H TFFE t 0 0 0 0 8 0 9 flash4- 23 B DFFE t 1 0 1 0 8 1 0 memtrg- 98 G SOFT s t 1 0 1 0 12 1 0 ob~1- 100 G SOFT s t 1 0 1 0 12 1 0 ob~2(68) 105 G SOFT s t 1 0 1 0 9 1 0 ob~3- 121 H SOFT s t 1 0 1 0 12 1 0 og~1- 122 H SOFT s t 1 0 1 0 12 1 0 og~2- 114 H SOFT s t 1 0 1 0 9 1 0 og~3(60) 93 F SOFT s t 1 0 1 0 12 1 0 orr~1(61) 94 F SOFT s t 1 0 1 0 12 1 0 orr~2- 84 F SOFT s t 1 0 1 0 9 1 0 orr~3- 44 C TFFE t 0 0 0 0 2 5 16 penttrg2- 4 A DFFE t 0 0 0 4 1 12 33 porteff70- 2 A DFFE t 0 0 0 4 1 5 6 porteff71(6) 13 A DFFE t 0 0 0 4 1 2 1 porteff72- 34 C DFFE t 0 0 0 4 1 0 1 porteff73- 7 A DFFE t 0 0 0 4 1 7 5 porteff74- 12 A DFFE t 0 0 0 3 0 1 2 portfe0(8) 11 A DFFE t 0 0 0 3 0 1 2 portfe1- 15 A DFFE t 0 0 0 3 0 1 2 portfe2- 1 A DFFE t 1 1 0 4 3 1 0 port7ffd0- 9 A DFFE t 1 1 0 4 3 1 0 port7ffd1- 10 A DFFE t 1 1 0 4 3 1 0 port7ffd2- 36 C DFFE t 1 1 0 4 3 3 6 port7ffd5(9) 8 A DFFE t 1 1 0 4 3 1 0 port7ffd6- 41 C DFFE t 1 1 0 4 3 1 0 port7ffd7- 18 B DFFE t 2 2 0 0 4 1 3 raml0- 31 B DFFE t 2 2 0 0 4 1 3 raml1(15) 29 B DFFE t 2 2 0 0 4 1 3 raml2(21) 19 B DFFE t 2 2 0 0 4 1 3 raml3(14) 32 B DFFE t 2 2 0 0 4 1 3 raml4(40) 51 D DFFE t 2 2 0 0 4 1 3 raml5(34) 61 D DFFE t 2 2 0 0 4 1 0 raml6(35) 59 D DFFE t 2 2 0 0 4 1 9 raml7- 58 D DFFE t 2 2 0 1 4 0 1 ramo0(23) 48 C DFFE t 2 2 0 1 4 0 1 ramo1(36) 57 D DFFE t 2 2 0 1 4 0 1 ramo2- 55 D DFFE t 2 2 0 1 4 0 1 ramo3- 50 D DFFE t 2 2 0 1 4 0 1 ramo4- 60 D DFFE t 2 2 0 1 4 0 1 ramo5(37) 56 D DFFE t 2 2 0 1 4 0 1 ramo6- 54 D DFFE t 2 2 0 1 4 0 1 ramo7- 33 C DFFE t 2 2 0 1 4 0 1 ramq0- 47 C DFFE t 2 2 0 1 4 0 1 ramq1(33) 64 D DFFE t 2 2 0 1 4 0 1 ramq2- 52 D DFFE t 2 2 0 1 4 0 1 ramq3(41) 49 D DFFE t 2 2 0 1 4 0 1 ramq4- 63 D DFFE t 2 2 0 1 4 0 1 ramq5- 62 D DFFE t 2 2 0 1 4 0 1 ramq6(39) 53 D DFFE t 2 2 0 1 4 0 1 ramq7- 81 F DFFE t 0 0 0 0 5 0 1 shift0- 82 F DFFE t 0 0 0 0 6 0 1 shift1- 92 F DFFE t 0 0 0 0 6 0 1 shift2- 108 G DFFE t 0 0 0 0 6 0 1 shift3- 89 F DFFE t 0 0 0 0 6 0 1 shift4- 20 B DFFE t 0 0 0 0 6 0 1 shift5- 106 G DFFE t 0 0 0 0 6 0 1 shift6- 22 B DFFE t 0 0 0 0 6 0 9 shift7(62) 96 F TFFE + t 0 0 0 0 0 5 10 trig0- 111 G TFFE t 0 0 0 0 1 6 26 trig1(63) 97 G DFFE t 0 0 0 2 2 2 0 trig4- 39 C DFFE t 3 0 0 5 3 1 0 trig5Code:s = Synthesized pin or logic cellt = Turbo logic cell+ = Synchronous flipflop/ = Slow slew-rate output! = NOT gate push-backr = Fitter-inserted logic cellDevice-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'A':Logic cells placed in LAB 'A'+----------------------------- LC3 av1| +--------------------------- LC14 av15| | +------------------------- LC6 bright| | | +----------------------- LC5 int| | | | +--------------------- LC4 porteff70| | | | | +------------------- LC2 porteff71| | | | | | +----------------- LC13 porteff72| | | | | | | +--------------- LC7 porteff74| | | | | | | | +------------- LC12 portfe0| | | | | | | | | +----------- LC11 portfe1| | | | | | | | | | +--------- LC15 portfe2| | | | | | | | | | | +------- LC1 port7ffd0| | | | | | | | | | | | +----- LC9 port7ffd1| | | | | | | | | | | | | +--- LC10 port7ffd2| | | | | | | | | | | | | | +- LC8 port7ffd6| | | | | | | | | | | | | | || | | | | | | | | | | | | | | Other LABs fed by signals| | | | | | | | | | | | | | | that feed LAB 'A'LC | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'A':LC4 -> - - * - - - - - - - - - - - - | * * * * * * * * | <-- porteff70LC2 -> - * - - - - - - - - - * * * * | * - * - - - - - | <-- porteff71LC7 -> - - * - - - - - - - - - - - - | * * - - * * * * | <-- porteff74Pin61 -> - - - - * - - - * - - * - - - | * - - - - - - - | <-- d060 -> - - - - - - - - - * - - * - - | * - - - - - - - | <-- d164 -> - - - - - * - - - - * - - * - | * - - - - - - - | <-- d268 -> - * - - - - * - - - - - - - - | * - - - - - - - | <-- d365 -> - - - - - - - * - - - - - - * | * - - - - - - - | <-- d683 -> - - - - - - - - - - - - - - - | - - - - - - - - | <-- f142 -> - * - - * * * * - - - * * * * | * - * - - - - - | <-- iorq8 -> - * - - * * * * * * * * * * * | * - * - - - - - | <-- port19 -> - * - - * * * * * * * * * * * | * - * - - - - - | <-- port284 -> - - - - - - - - - - - - - - - | - - - - * - - - | <-- rd1 -> - - - - - - - - - - - - - - - | - - * - - - - - | <-- resLC88 -> * - - - - - - - - - - - - - - | * * - - - - - - | <-- av0LC25 -> - - - * - - - - - - - - - - - | * * - - * - - - | <-- av2LC24 -> - - - * - - - - - - - - - - - | * * - - * - - - | <-- av3LC17 -> - - * - - - - - - - - - - - - | * * - - * * - * | <-- av4LC123-> - - * * - - - - - - - - - - - | * * - - * * * * | <-- av6LC86 -> - - * * - - - - - - - - - - - | * * - - * * * * | <-- av7LC26 -> - - * - - - - - - - - - - - - | * - - - * * * * | <-- bordtrgLC109-> - * - - * * * * - - - * * * * | * - * - - - - - | <-- clkLC95 -> * - - - - - - - - - - - - - - | * * - * - * * - | <-- count11LC21 -> - - * - - - - - - - - - - - - | * * - - * * * * | <-- count23LC102-> - - * * - - - - - - - - - - - | * * - - * * * * | <-- count41LC112-> - - * * - - - - - - - - - - - | * * - - * * * * | <-- count42LC30 -> - - * - - - - - - - - - - - - | * * - - * * * * | <-- count43LC28 -> - - * - - - - - - - - - - - - | * - - - * * - * | <-- dsp~1LC36 -> - * - - - - - - - - - * * * * | * - * - - - - - | <-- port7ffd5LC61 -> - - * - - - - - - - - - - - - | * - - - - - - - | <-- raml6LC59 -> - - * - - - - - - - - - - - - | * - - - - * * * | <-- raml7LC96 -> - - * - - - - - - - - - - - - | * * - - * * * * | <-- trig0LC111-> * - * - - - - - - - - - - - - | * * - * * * * * | <-- trig1LC67 -> * - - - - - - - - - - - - - - | * * - - - * * - | <-- x2* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'B':Logic cells placed in LAB 'B'+------------------------------- LC25 av2| +----------------------------- LC24 av3| | +--------------------------- LC17 av4| | | +------------------------- LC26 bordtrg| | | | +----------------------- LC21 count23| | | | | +--------------------- LC30 count43| | | | | | +------------------- LC28 dsp~1| | | | | | | +----------------- LC23 memtrg| | | | | | | | +--------------- LC18 raml0| | | | | | | | | +------------- LC31 raml1| | | | | | | | | | +----------- LC29 raml2| | | | | | | | | | | +--------- LC19 raml3| | | | | | | | | | | | +------- LC32 raml4| | | | | | | | | | | | | +----- LC20 shift5| | | | | | | | | | | | | | +--- LC22 shift7| | | | | | | | | | | | | | | +- LC27 y0| | | | | | | | | | | | | | | || | | | | | | | | | | | | | | | Other LABs fed by signals| | | | | | | | | | | | | | | | that feed LAB 'B'LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'B':LC25 -> * * * - * - - - - - - - - - - - | * * - - * - - - | <-- av2LC24 -> * * * - * - * - - - - - - - - - | * * - - * - - - | <-- av3LC17 -> * * * - * - * - - - - - - - - - | * * - - * * - * | <-- av4LC21 -> * * * * * - * * - - - - - - - - | * * - - * * * * | <-- count23LC30 -> - - - * - * - * - - - - - - - - | * * - - * * * * | <-- count43Pin4 -> - - - - - - - - - - - - - - - * | - * * - * - - - | <-- a146 -> - - - - - - - - - - - - - - - * | - * * - * - - - | <-- a1583 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- f142 -> - - - - - - - - - - - - - - - - | * - * - - - - - | <-- iorq84 -> - - - - - - - - - - - - - - - - | - - - - * - - - | <-- rd1 -> - - - - - - - - - - - - - - - - | - - * - - - - - | <-- resLC88 -> * * * * * - - - - - - - - - - - | * * - - - - - - | <-- av0LC3 -> * * * - * - - - - - - - - - - - | - * - - - - - - | <-- av1LC123-> - - - - - * * - - - - - - - - - | * * - - * * * * | <-- av6LC86 -> - - - - - * * - - - - - - - - - | * * - - * * * * | <-- av7LC95 -> * * * - * - - * * * * * * * * - | * * - * - * * - | <-- count11LC102-> - - - * - * * * - - - - - - - - | * * - - * * * * | <-- count41LC112-> - - - * - * * * - - - - - - - - | * * - - * * * * | <-- count42LC72 -> - - - - - - - * - - - - - - - - | - * * * * - - - | <-- hlLC4 -> - - - - - - - - * * * * * - - - | * * * * * * * * | <-- porteff70LC7 -> - - - * - - - * - - - - - - - - | * * - - * * * * | <-- porteff74LC1 -> - - - - - - - - - - - - - - - * | - * - - - - - - | <-- port7ffd0LC58 -> - - - - - - - - * - - - - - - - | - * - - - - - - | <-- ramo0LC48 -> - - - - - - - - - * - - - - - - | - * - - - - - - | <-- ramo1LC57 -> - - - - - - - - - - * - - - - - | - * - - - - - - | <-- ramo2LC55 -> - - - - - - - - - - - * - - - - | - * - - - - - - | <-- ramo3LC50 -> - - - - - - - - - - - - * - - - | - * - - - - - - | <-- ramo4LC63 -> - - - - - - - - - - - - - * - - | - * - - - - - - | <-- ramq5LC53 -> - - - - - - - - - - - - - - * - | - * - - - - - - | <-- ramq7LC89 -> - - - - - - - - - - - - - * - - | - * - - - - - - | <-- shift4LC106-> - - - - - - - - - - - - - - * - | - * - - - - - - | <-- shift6LC96 -> - - - - - - - - - - - - - * * - | * * - - * * * * | <-- trig0LC111-> - - - - - - - - * * * * * * * - | * * - * * * * * | <-- trig1LC67 -> * * * - * - - * - - - - - * * - | * * - - - * * - | <-- x2* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'C':Logic cells placed in LAB 'C'+------------------------------- LC46 csos| +----------------------------- LC42 delay| | +--------------------------- LC37 mem0| | | +------------------------- LC40 mem1| | | | +----------------------- LC43 mem2| | | | | +--------------------- LC45 mem3| | | | | | +------------------- LC44 penttrg2| | | | | | | +----------------- LC34 porteff73| | | | | | | | +--------------- LC36 port7ffd5| | | | | | | | | +------------- LC41 port7ffd7| | | | | | | | | | +----------- LC48 ramo1| | | | | | | | | | | +--------- LC33 ramq0| | | | | | | | | | | | +------- LC47 ramq1| | | | | | | | | | | | | +----- LC39 trig5| | | | | | | | | | | | | | +--- LC38 wait| | | | | | | | | | | | | | | +- LC35 y1| | | | | | | | | | | | | | | || | | | | | | | | | | | | | | | Other LABs fed by signals| | | | | | | | | | | | | | | | that feed LAB 'C'LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'C':LC42 -> - * - - - - - - - - - - - - * - | - - * - - - - - | <-- delayLC44 -> - - - - - - * - - - * * * - - - | - - * * - - - * | <-- penttrg2LC36 -> * - * - - - - - * * - - - - - - | * - * - - - - - | <-- port7ffd5LC41 -> - - - - - * - - - - - - - - - - | - - * - - - - - | <-- port7ffd7LC39 -> - - - - - - - - - - - - - - * - | - - * - - - - - | <-- trig5Pin4 -> - - * * * * - - - - - - - * - * | - * * - * - - - | <-- a146 -> - - * * * * - - - - - - - * - * | - * * - * - - - | <-- a1569 -> * - - - - - - * - - - - - - - - | - - * - - - - - | <-- d467 -> - - - - - - - - * - - - - - - - | - - * - - - - - | <-- d563 -> - - - - - - - - - * - - - - - - | - - * - - - - - | <-- d783 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- f142 -> * * - - - - - * * * - - - - - - | * - * - - - - - | <-- iorq20 -> - - - - - - - - - - - - - * - - | - - * - * - - - | <-- mreq8 -> * - - - - - - * * * - - - - - - | * - * - - - - - | <-- port19 -> * - - - - - - * * * - - - - - - | * - * - - - - - | <-- port233 -> - - - - - - - - - - - * - - - - | - - * * - - - - | <-- ram034 -> - - - - - - - - - - * - * - - - | - - * - - - - - | <-- ram184 -> - - - - - - - - - - - - - - - - | - - - - * - - - | <-- rd1 -> - - - - - - - - - - - - - * - - | - - * - - - - - | <-- res21 -> - - - - - - - - - - - - - * - - | - - * - * - * - | <-- rfshLC75 -> - - - - - - * - - - - - - * - - | - - * - * - - - | <-- casLC109-> * * - - - - - * * * - - - - - - | * - * - - - - - | <-- clkLC72 -> - - - * - - * - - - * * * * - - | - * * * * - - - | <-- hlLC4 -> - - - - - - - - - - * * * - - - | * * * * * * * * | <-- porteff70LC2 -> * - * - * * - - * * - - - - - - | * - * - - - - - | <-- porteff71LC13 -> - - - - - - - - - - - - - * - - | - - * - * - - - | <-- porteff72LC9 -> - - - - - - - - - - - - - - - * | - - * - - - - - | <-- port7ffd1LC10 -> - - - * - - - - - - - - - - - - | - - * - - - - - | <-- port7ffd2LC8 -> - - - - * - - - - - - - - - - - | - - * - - - - - | <-- port7ffd6LC73 -> - - - - - - - - - - * * * - - - | - - * * * - - - | <-- rasLC97 -> - - - - - - - - - - - - - - * - | - - * - - - * - | <-- trig4* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'D':Logic cells placed in LAB 'D'+------------------------------- LC51 raml5| +----------------------------- LC61 raml6| | +--------------------------- LC59 raml7| | | +------------------------- LC58 ramo0| | | | +----------------------- LC57 ramo2| | | | | +--------------------- LC55 ramo3| | | | | | +------------------- LC50 ramo4| | | | | | | +----------------- LC60 ramo5| | | | | | | | +--------------- LC56 ramo6| | | | | | | | | +------------- LC54 ramo7| | | | | | | | | | +----------- LC64 ramq2| | | | | | | | | | | +--------- LC52 ramq3| | | | | | | | | | | | +------- LC49 ramq4| | | | | | | | | | | | | +----- LC63 ramq5| | | | | | | | | | | | | | +--- LC62 ramq6| | | | | | | | | | | | | | | +- LC53 ramq7| | | | | | | | | | | | | | | || | | | | | | | | | | | | | | | Other LABs fed by signals| | | | | | | | | | | | | | | | that feed LAB 'D'LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'D':LC60 -> * - - - - - - - - - - - - - - - | - - - * - - - - | <-- ramo5LC56 -> - * - - - - - - - - - - - - - - | - - - * - - - - | <-- ramo6LC54 -> - - * - - - - - - - - - - - - - | - - - * - - - - | <-- ramo7Pin83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- f142 -> - - - - - - - - - - - - - - - - | * - * - - - - - | <-- iorq33 -> - - - * - - - - - - - - - - - - | - - * * - - - - | <-- ram035 -> - - - - * - - - - - * - - - - - | - - - * - - - - | <-- ram236 -> - - - - - * - - - - - * - - - - | - - - * - - - - | <-- ram337 -> - - - - - - * - - - - - * - - - | - - - * - - - - | <-- ram439 -> - - - - - - - * - - - - - * - - | - - - * - - - - | <-- ram540 -> - - - - - - - - * - - - - - * - | - - - * - - - - | <-- ram641 -> - - - - - - - - - * - - - - - * | - - - * - - - - | <-- ram784 -> - - - - - - - - - - - - - - - - | - - - - * - - - | <-- rd1 -> - - - - - - - - - - - - - - - - | - - * - - - - - | <-- resLC95 -> * * * - - - - - - - - - - - - - | * * - * - * * - | <-- count11LC72 -> - - - * * * * * * * * * * * * * | - * * * * - - - | <-- hlLC44 -> - - - * * * * * * * * * * * * * | - - * * - - - * | <-- penttrg2LC4 -> * * * * * * * * * * * * * * * * | * * * * * * * * | <-- porteff70LC73 -> - - - * * * * * * * * * * * * * | - - * * * - - - | <-- rasLC111-> * * * - - - - - - - - - - - - - | * * - * * * * * | <-- trig1* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'E':Logic cells placed in LAB 'E'+----------------- LC65 b| +--------------- LC77 busrq| | +------------- LC75 cas| | | +----------- LC66 countstr| | | | +--------- LC72 hl| | | | | +------- LC73 ras| | | | | | +----- LC80 sync| | | | | | | +--- LC69 we| | | | | | | | +- LC67 x2| | | | | | | | || | | | | | | | | Other LABs fed by signals| | | | | | | | | that feed LAB 'E'LC | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'E':LC75 -> - - - - * - - - - | - - * - * - - - | <-- casLC72 -> - - - - * - - * - | - * * * * - - - | <-- hlLC73 -> - - * - - - - - - | - - * * * - - - | <-- rasPin4 -> - - - - * - - * - | - * * - * - - - | <-- a146 -> - - - - * - - * - | - * * - * - - - | <-- a1583 -> - - - - - - - - - | - - - - - - - - | <-- f142 -> - - - - - - - - - | * - * - - - - - | <-- iorq20 -> - - - - * - - * - | - - * - * - - - | <-- mreq84 -> - - - - - - - * - | - - - - * - - - | <-- rd1 -> - - - - - - - - - | - - * - - - - - | <-- res21 -> - - - - * - - - - | - - * - * - * - | <-- rfshLC25 -> - - - * - - * - - | * * - - * - - - | <-- av2LC24 -> - - - * - - * - - | * * - - * - - - | <-- av3LC17 -> * - - - - - - - - | * * - - * * - * | <-- av4LC123-> * - - - - - * - - | * * - - * * * * | <-- av6LC86 -> * - - - - - * - - | * * - - * * * * | <-- av7LC26 -> * - - - - - - - - | * - - - * * * * | <-- bordtrgLC21 -> * * - * - - * - - | * * - - * * * * | <-- count23LC102-> * * - - - - * - - | * * - - * * * * | <-- count41LC112-> * * - - - - * - - | * * - - * * * * | <-- count42LC30 -> * * - - - - - - - | * * - - * * * * | <-- count43LC28 -> * - - - - - - - - | * - - - * * - * | <-- dsp~1LC23 -> - - - - * - - - - | - - - - * - - - | <-- memtrgLC98 -> * - - - - - - - - | - - - - * - - - | <-- ob~1LC100-> * - - - - - - - - | - - - - * - - - | <-- ob~2LC105-> * - - - - - - - - | - - - - * - - - | <-- ob~3LC4 -> * * - - - - - - - | * * * * * * * * | <-- porteff70LC13 -> - - - - * - - * - | - - * - * - - - | <-- porteff72LC7 -> * * - - - - - - - | * * - - * * * * | <-- porteff74LC12 -> * - - - - - - - - | - - - - * - * - | <-- portfe0LC18 -> * - - - - - - - - | - - - - * - * - | <-- raml0LC19 -> * - - - - - - - - | - - - - * - * - | <-- raml3LC96 -> * - - - - - - - - | * * - - * * * * | <-- trig0LC111-> - - - - - * - - * | * * - * * * * * | <-- trig1* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'F':Logic cells placed in LAB 'F'+--------------------------- LC88 av0| +------------------------- LC86 av7| | +----------------------- LC91 av13| | | +--------------------- LC83 av14| | | | +------------------- LC95 count11| | | | | +----------------- LC93 orr~1| | | | | | +--------------- LC94 orr~2| | | | | | | +------------- LC84 orr~3| | | | | | | | +----------- LC85 r| | | | | | | | | +--------- LC81 shift0| | | | | | | | | | +------- LC82 shift1| | | | | | | | | | | +----- LC92 shift2| | | | | | | | | | | | +--- LC89 shift4| | | | | | | | | | | | | +- LC96 trig0| | | | | | | | | | | | | || | | | | | | | | | | | | | Other LABs fed by signals| | | | | | | | | | | | | | that feed LAB 'F'LC | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'F':LC86 -> - * - - - - - - * - - - - - | * * - - * * * * | <-- av7LC95 -> * - * - * - - - - * * * * - | * * - * - * * - | <-- count11LC93 -> - - - - - - - - * - - - - - | - - - - - * - - | <-- orr~1LC94 -> - - - - - - - - * - - - - - | - - - - - * - - | <-- orr~2LC84 -> - - - - - - - - * - - - - - | - - - - - * - - | <-- orr~3LC81 -> - - - - - - - - - - * - - - | - - - - - * - - | <-- shift0LC82 -> - - - - - - - - - - - * - - | - - - - - * - - | <-- shift1LC96 -> - - - - - - - - * * * * * * | * * - - * * * * | <-- trig0Pin83 -> - - - - - - - - - - - - - - | - - - - - - - - | <-- f142 -> - - - - - - - - - - - - - - | * - * - - - - - | <-- iorq84 -> - - - - - - - - - - - - - - | - - - - * - - - | <-- rd1 -> - - - - - - - - - - - - - - | - - * - - - - - | <-- resLC17 -> - - - - - - - - * - - - - - | * * - - * * - * | <-- av4LC123-> - * - - - - - - * - - - - - | * * - - * * * * | <-- av6LC26 -> - - - - - * * * * - - - - - | * - - - * * * * | <-- bordtrgLC21 -> - - * - - * - - * - - - - - | * * - - * * * * | <-- count23LC102-> - * - * - * * - * - - - - - | * * - - * * * * | <-- count41LC112-> - * - * - * * - * - - - - - | * * - - * * * * | <-- count42LC30 -> - * - * - * - - * - - - - - | * * - - * * * * | <-- count43LC28 -> - - - - - - - - * - - - - - | * - - - * * - * | <-- dsp~1LC113-> - - - - - * * * - - - - - - | - - - - - * * * | <-- flash4LC4 -> - - * * - * * * * - - - - - | * * * * * * * * | <-- porteff70LC7 -> - - * * - - * - * - - - - - | * * - - * * * * | <-- porteff74LC11 -> - - - - - - * * * - - - - - | - - - - - * - - | <-- portfe1LC31 -> - - - - - * * * * - - - - - | - - - - - * - - | <-- raml1LC32 -> - - - - - * * * * - - - - - | - - - - - * - - | <-- raml4LC59 -> - - - - - * * * - - - - - - | * - - - - * * * | <-- raml7LC33 -> - - - - - - - - - * - - - - | - - - - - * - - | <-- ramq0LC47 -> - - - - - - - - - - * - - - | - - - - - * - - | <-- ramq1LC64 -> - - - - - - - - - - - * - - | - - - - - * - - | <-- ramq2LC49 -> - - - - - - - - - - - - * - | - - - - - * - - | <-- ramq4LC108-> - - - - - - - - - - - - * - | - - - - - * - - | <-- shift3LC22 -> - - - - - * * * - - - - - - | - - - - - * * * | <-- shift7LC111-> * - - - * * * * - * * * * - | * * - * * * * * | <-- trig1LC67 -> * - - * * - - - - * * * * - | * * - - - * * - | <-- x2* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'G':Logic cells placed in LAB 'G'+----------------------- LC109 clk| +--------------------- LC102 count41| | +------------------- LC112 count42| | | +----------------- LC107 flash0| | | | +--------------- LC99 flash1| | | | | +------------- LC98 ob~1| | | | | | +----------- LC100 ob~2| | | | | | | +--------- LC105 ob~3| | | | | | | | +------- LC108 shift3| | | | | | | | | +----- LC106 shift6| | | | | | | | | | +--- LC111 trig1| | | | | | | | | | | +- LC97 trig4| | | | | | | | | | | || | | | | | | | | | | | Other LABs fed by signals| | | | | | | | | | | | that feed LAB 'G'LC | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'G':LC102-> - * * * * * * - - - - - | * * - - * * * * | <-- count41LC112-> - * * * * * * - - - - - | * * - - * * * * | <-- count42LC107-> - - - * * - - - - - - - | - - - - - - * * | <-- flash0LC111-> * - - - - * * * * * * - | * * - * * * * * | <-- trig1LC97 -> * - - - - - - - - - - - | - - * - - - * - | <-- trig4Pin15 -> - - - - - - - - - - - * | - - - - - - * - | <-- dos83 -> - - - - - - - - - - - - | - - - - - - - - | <-- f142 -> - - - - - - - - - - - - | * - * - - - - - | <-- iorq84 -> - - - - - - - - - - - - | - - - - * - - - | <-- rd1 -> - - - - - - - - - - - - | - - * - - - - - | <-- res21 -> - - - - - - - - - - - * | - - * - * - * - | <-- rfshLC123-> - * * * * - - - - - - - | * * - - * * * * | <-- av6LC86 -> - * * * * - - - - - - - | * * - - * * * * | <-- av7LC26 -> - - - - - * * * - - - - | * - - - * * * * | <-- bordtrgLC95 -> - - - - - - - - * * - - | * * - * - * * - | <-- count11LC21 -> - - - - - * - - - - - - | * * - - * * * * | <-- count23LC30 -> - * * - - * - - - - - - | * * - - * * * * | <-- count43LC113-> - - - - - * * * - - - - | - - - - - * * * | <-- flash4LC4 -> - - - - - * * * - - - - | * * * * * * * * | <-- porteff70LC34 -> - - - - - - - - - - - * | - - - - - - * - | <-- porteff73LC7 -> - - - - - - * - - - - - | * * - - * * * * | <-- porteff74LC12 -> - - - - - - * * - - - - | - - - - * - * - | <-- portfe0LC18 -> - - - - - * * * - - - - | - - - - * - * - | <-- raml0LC19 -> - - - - - * * * - - - - | - - - - * - * - | <-- raml3LC59 -> - - - - - * * * - - - - | * - - - - * * * | <-- raml7LC52 -> - - - - - - - - * - - - | - - - - - - * - | <-- ramq3LC62 -> - - - - - - - - - * - - | - - - - - - * - | <-- ramq6LC92 -> - - - - - - - - * - - - | - - - - - - * - | <-- shift2LC20 -> - - - - - - - - - * - - | - - - - - - * - | <-- shift5LC22 -> - - - - - * * * - - - - | - - - - - * * * | <-- shift7LC96 -> * - - - - - - - * * * * | * * - - * * * * | <-- trig0LC67 -> - - - - - - - - * * - - | * * - - - * * - | <-- x2* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** LOGIC CELL INTERCONNECTIONS **Logic Array Block 'H':Logic cells placed in LAB 'H'+------------------------------- LC115 av5| +----------------------------- LC123 av6| | +--------------------------- LC120 av8| | | +------------------------- LC118 av9| | | | +----------------------- LC117 av10| | | | | +--------------------- LC128 av11| | | | | | +------------------- LC126 av12| | | | | | | +----------------- LC119 count30| | | | | | | | +--------------- LC124 count31| | | | | | | | | +------------- LC116 flash2| | | | | | | | | | +----------- LC127 flash3| | | | | | | | | | | +--------- LC113 flash4| | | | | | | | | | | | +------- LC125 g| | | | | | | | | | | | | +----- LC121 og~1| | | | | | | | | | | | | | +--- LC122 og~2| | | | | | | | | | | | | | | +- LC114 og~3| | | | | | | | | | | | | | | || | | | | | | | | | | | | | | | Other LABs fed by signals| | | | | | | | | | | | | | | | that feed LAB 'H'LC | | | | | | | | | | | | | | | | | A B C D E F G H | Logic cells that feed LAB 'H':LC115-> * * - - - - - - - - - - - - - - | - - - - - - - * | <-- av5LC123-> - * - - - - - - - * * * * - - - | * * - - * * * * | <-- av6LC119-> * * - * - - - * * - - - - - - - | - - - - - - - * | <-- count30LC124-> * * - - * - - - * - - - - - - - | - - - - - - - * | <-- count31LC116-> - - - - - - - - - * * * - - - - | - - - - - - - * | <-- flash2LC127-> - - - - - - - - - - * * - - - - | - - - - - - - * | <-- flash3LC113-> - - - - - - - - - - - * - * * * | - - - - - * * * | <-- flash4LC121-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- og~1LC122-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- og~2LC114-> - - - - - - - - - - - - * - - - | - - - - - - - * | <-- og~3Pin83 -> - - - - - - - - - - - - - - - - | - - - - - - - - | <-- f142 -> - - - - - - - - - - - - - - - - | * - * - - - - - | <-- iorq84 -> - - - - - - - - - - - - - - - - | - - - - * - - - | <-- rd1 -> - - - - - - - - - - - - - - - - | - - * - - - - - | <-- resLC17 -> - - - - - - - - - - - - * - - - | * * - - * * - * | <-- av4LC86 -> - - - - - - - - - * * * * - - - | * * - - * * * * | <-- av7LC26 -> - - - - - - - - - - - - * * * * | * - - - * * * * | <-- bordtrgLC66 -> * * * - - - - * * - - - - - - - | - - - - - - - * | <-- countstrLC21 -> - - - - - - - - - - - - * * - - | * * - - * * * * | <-- count23LC102-> - - * - - * - - - * * * * * * - | * * - - * * * * | <-- count41LC112-> - - - * - * * - - * * * * * * - | * * - - * * * * | <-- count42LC30 -> - - - - - * - - - - - - * * - - | * * - - * * * * | <-- count43LC28 -> - - - - - - - - - - - - * - - - | * - - - * * - * | <-- dsp~1LC107-> - - - - - - - - - * * * - - - - | - - - - - - * * | <-- flash0LC99 -> - - - - - - - - - * * * - - - - | - - - - - - - * | <-- flash1LC44 -> - - * * * * * - - - - - - - - - | - - * * - - - * | <-- penttrg2LC4 -> - - * * * * * - - - - - * * * * | * * * * * * * * | <-- porteff70LC7 -> - - - - - - - - - - - - * - * - | * * - - * * * * | <-- porteff74LC15 -> - - - - - - - - - - - - * - * * | - - - - - - - * | <-- portfe2LC29 -> - - - - - - - - - - - - * * * * | - - - - - - - * | <-- raml2LC51 -> - - - - - - - - - - - - * * * * | - - - - - - - * | <-- raml5LC59 -> - - - - - - - - - - - - - * * * | * - - - - * * * | <-- raml7LC22 -> - - - - - - - - - - - - - * * * | - - - - - * * * | <-- shift7LC96 -> - - - - - - - - - - - - * - - - | * * - - * * * * | <-- trig0LC111-> - - - - - - - - - - - - - * * * | * * - * * * * * | <-- trig1* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.- = The logic cell or pin is not an input to the logic cell (or LAB).Device-Specific Information: c:\final\p1024sl.rptp1024sl** EQUATIONS **a14 : INPUT;a15 : INPUT;dos : INPUT;d0 : INPUT;d1 : INPUT;d2 : INPUT;d3 : INPUT;d4 : INPUT;d5 : INPUT;d6 : INPUT;d7 : INPUT;f14 : INPUT;iorq : INPUT;mreq : INPUT;port1 : INPUT;port2 : INPUT;ram0 : INPUT;ram1 : INPUT;ram2 : INPUT;ram3 : INPUT;ram4 : INPUT;ram5 : INPUT;ram6 : INPUT;ram7 : INPUT;rd : INPUT;res : INPUT;rfsh : INPUT;-- Node name is 'av0' = 'count12' from file "p1024sl.tdf" line 24, column 19-- Equation name is 'av0', location is LC088, type is output.av0 = TFFE( _EQ001, trig1, VCC, VCC, VCC);_EQ001 = count11 & x2;-- Node name is 'av1' = 'count13' from file "p1024sl.tdf" line 24, column 19-- Equation name is 'av1', location is LC003, type is output.av1 = TFFE( _EQ002, trig1, VCC, VCC, VCC);_EQ002 = av0 & count11 & x2;-- Node name is 'av2' = 'count20' from file "p1024sl.tdf" line 24, column 33-- Equation name is 'av2', location is LC025, type is output.av2 = TFFE(!_EQ003, _EQ004, VCC, VCC, VCC);_EQ003 = av2 & av3 & av4 & count23;_EQ004 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &_X008;_X001 = EXP(!av0 & av2 & av3 & av4 & count23);_X002 = EXP(!av1 & av2 & av3 & av4 & count23);_X003 = EXP( av2 & av3 & av4 & !count11 & count23);_X004 = EXP( av2 & av3 & av4 & count23 & !x2);_X005 = EXP( av0 & av1 & !av2 & count11 & x2);_X006 = EXP( av0 & av1 & !av3 & count11 & x2);_X007 = EXP( av0 & av1 & !av4 & count11 & x2);_X008 = EXP( av0 & av1 & count11 & !count23 & x2);-- Node name is 'av3' = 'count21' from file "p1024sl.tdf" line 24, column 33-- Equation name is 'av3', location is LC024, type is output.av3 = TFFE( av2, _EQ005, VCC, VCC, VCC);_EQ005 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &_X008;_X001 = EXP(!av0 & av2 & av3 & av4 & count23);_X002 = EXP(!av1 & av2 & av3 & av4 & count23);_X003 = EXP( av2 & av3 & av4 & !count11 & count23);_X004 = EXP( av2 & av3 & av4 & count23 & !x2);_X005 = EXP( av0 & av1 & !av2 & count11 & x2);_X006 = EXP( av0 & av1 & !av3 & count11 & x2);_X007 = EXP( av0 & av1 & !av4 & count11 & x2);_X008 = EXP( av0 & av1 & count11 & !count23 & x2);-- Node name is 'av4' = 'count22' from file "p1024sl.tdf" line 24, column 33-- Equation name is 'av4', location is LC017, type is output.av4 = TFFE( _EQ006, _EQ007, VCC, VCC, VCC);_EQ006 = av2 & av3;_EQ007 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &_X008;_X001 = EXP(!av0 & av2 & av3 & av4 & count23);_X002 = EXP(!av1 & av2 & av3 & av4 & count23);_X003 = EXP( av2 & av3 & av4 & !count11 & count23);_X004 = EXP( av2 & av3 & av4 & count23 & !x2);_X005 = EXP( av0 & av1 & !av2 & count11 & x2);_X006 = EXP( av0 & av1 & !av3 & count11 & x2);_X007 = EXP( av0 & av1 & !av4 & count11 & x2);_X008 = EXP( av0 & av1 & count11 & !count23 & x2);-- Node name is 'av5' = 'count32' from file "p1024sl.tdf" line 24, column 47-- Equation name is 'av5', location is LC115, type is output.av5 = TFFE( _EQ008, countstr, VCC, VCC, VCC);_EQ008 = count30 & count31;-- Node name is 'av6' = 'count33' from file "p1024sl.tdf" line 24, column 47-- Equation name is 'av6', location is LC123, type is output.av6 = TFFE( _EQ009, countstr, VCC, VCC, VCC);_EQ009 = av5 & count30 & count31;-- Node name is 'av7' = 'count40' from file "p1024sl.tdf" line 25, column 7-- Equation name is 'av7', location is LC086, type is output.av7 = TFFE(!_EQ010, !av6, !_EQ011, VCC, VCC);_EQ010 = !av7 & count41 & !count42 & count43;_EQ011 = count41 & !count42 & count43;-- Node name is 'av8'-- Equation name is 'av8', location is LC120, type is output.av8 = LCELL( _EQ012 $ !countstr);_EQ012 = countstr & count41 & penttrg2 & !porteff70# !countstr & !count41 & penttrg2 & !porteff70;-- Node name is 'av9'-- Equation name is 'av9', location is LC118, type is output.av9 = LCELL( _EQ013 $ count30);_EQ013 = !count30 & count42 & penttrg2 & !porteff70# count30 & !count42 & penttrg2 & !porteff70;-- Node name is 'av10'-- Equation name is 'av10', location is LC117, type is output.av10 = LCELL( _EQ014 $ count31);_EQ014 = count31 & penttrg2 & !porteff70;-- Node name is 'av11'-- Equation name is 'av11', location is LC128, type is output.av11 = LCELL( _EQ015 $ count41);_EQ015 = count41 & count42 & penttrg2 & !porteff70# count41 & count43 & penttrg2 & !porteff70# !count41 & !count43 & penttrg2 & !porteff70;-- Node name is 'av12'-- Equation name is 'av12', location is LC126, type is output.av12 = LCELL( _EQ016 $ count42);_EQ016 = !count42 & penttrg2 & !porteff70;-- Node name is 'av13'-- Equation name is 'av13', location is LC091, type is output.av13 = LCELL( _EQ017 $ GND);_EQ017 = count11 & porteff70 & !porteff74# count23 & porteff74;-- Node name is 'av14'-- Equation name is 'av14', location is LC083, type is output.av14 = LCELL( _EQ018 $ !porteff74);_EQ018 = !count42 & !count43 & porteff74# !count41 & !count43 & porteff74# porteff70 & !porteff74 & !x2;-- Node name is 'av15' = 'port7ffd3' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'av15', location is LC014, type is output.av15 = DFFE( d3 $ GND, _EQ019, GLOBAL( res), VCC, VCC);_EQ019 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'b' = 'brgout0' from file "p1024sl.tdf" line 27, column 70-- Equation name is 'b', location is LC065, type is output.b = DFFE( _EQ020 $ VCC, !trig0, !_EQ021, VCC, VCC);_EQ020 = !_LC098 & !_LC100 & !_LC105 & _X010 & _X011 & _X012 & _X013 &_X014;_X010 = EXP( count43 & porteff70 & !porteff74 & portfe0);_X011 = EXP(!bordtrg & !porteff70 & raml0 & raml3);_X012 = EXP(!count23 & porteff70 & !porteff74 & portfe0);_X013 = EXP( portfe0 & raml0 & raml3);_X014 = EXP( bordtrg & portfe0);_EQ021 = !_LC028 & _X015 & _X016 & _X017 & _X018 & _X019 & _X020 &_X021 & _X022;_X015 = EXP(!av6 & count23);_X016 = EXP(!av7 & count23);_X017 = EXP( count23 & !count41);_X018 = EXP( count23 & !count42);_X019 = EXP(!av4 & !av6);_X020 = EXP(!av4 & !av7);_X021 = EXP(!av4 & !count41);_X022 = EXP(!av4 & !count42);-- Node name is 'bordtrg' from file "p1024sl.tdf" line 25, column 25-- Equation name is 'bordtrg', location is LC026, type is buried.bordtrg = DFFE( _EQ022 $ !porteff74, av0, VCC, VCC, VCC);_EQ022 = count23 & !count41 & !count43 & !porteff74# count23 & !count42 & !count43 & !porteff74;-- Node name is 'bright' = 'brgout3' from file "p1024sl.tdf" line 27, column 70-- Equation name is 'bright', location is LC006, type is output.bright = DFFE( _EQ023 $ _EQ024, !trig0, !_EQ025, VCC, VCC);_EQ023 = !bordtrg & count41 & count42 & porteff70 & !porteff74 & _X023 &_X024 & _X025 & _X026# !bordtrg & count43 & porteff70 & !porteff74 & _X023 & _X024 &_X025 & _X026;_X023 = EXP( porteff70 & !raml7 & !trig1);_X024 = EXP(!count23 & porteff70 & !porteff74);_X025 = EXP(!raml6 & trig1);_X026 = EXP(!porteff70 & !raml6);_EQ024 = !bordtrg & _X023 & _X024 & _X025 & _X026;_X023 = EXP( porteff70 & !raml7 & !trig1);_X024 = EXP(!count23 & porteff70 & !porteff74);_X025 = EXP(!raml6 & trig1);_X026 = EXP(!porteff70 & !raml6);_EQ025 = !_LC028 & _X015 & _X016 & _X017 & _X018 & _X019 & _X020 &_X021 & _X022;_X015 = EXP(!av6 & count23);_X016 = EXP(!av7 & count23);_X017 = EXP( count23 & !count41);_X018 = EXP( count23 & !count42);_X019 = EXP(!av4 & !av6);_X020 = EXP(!av4 & !av7);_X021 = EXP(!av4 & !count41);_X022 = EXP(!av4 & !count42);-- Node name is 'busrq'-- Equation name is 'busrq', location is LC077, type is output.busrq = LCELL( _EQ026 $ VCC);_EQ026 = count23 & !count42 & !count43 & porteff70# count23 & !count41 & !count43 & porteff70# porteff70 & porteff74;-- Node name is 'cas' = 'trig3' from file "p1024sl.tdf" line 24, column 5-- Equation name is 'cas', location is LC075, type is output.cas = trig3~NOT;trig3~NOT = DFFE(!ras $ VCC, GLOBAL(!f14), VCC, VCC, VCC);-- Node name is 'clk' = 'trig6' from file "p1024sl.tdf" line 24, column 5-- Equation name is 'clk', location is LC109, type is output.clk = DFFE( _EQ027 $ GND, GLOBAL( f14), VCC, VCC, VCC);_EQ027 = !trig1 & trig4# trig0 & !trig4;-- Node name is 'countstr' from file "p1024sl.tdf" line 25, column 15-- Equation name is 'countstr', location is LC066, type is buried.countstr = TFFE( VCC, _EQ028, VCC, VCC, VCC);_EQ028 = !av2 & !av3 & !count23;-- Node name is 'count11' from file "p1024sl.tdf" line 24, column 19-- Equation name is 'count11', location is LC095, type is buried.count11 = TFFE( x2, trig1, VCC, VCC, VCC);-- Node name is 'count23' from file "p1024sl.tdf" line 24, column 33-- Equation name is 'count23', location is LC021, type is buried.count23 = TFFE( _EQ029, _EQ030, VCC, VCC, VCC);_EQ029 = av2 & av3 & av4;_EQ030 = _X001 & _X002 & _X003 & _X004 & _X005 & _X006 & _X007 &_X008;_X001 = EXP(!av0 & av2 & av3 & av4 & count23);_X002 = EXP(!av1 & av2 & av3 & av4 & count23);_X003 = EXP( av2 & av3 & av4 & !count11 & count23);_X004 = EXP( av2 & av3 & av4 & count23 & !x2);_X005 = EXP( av0 & av1 & !av2 & count11 & x2);_X006 = EXP( av0 & av1 & !av3 & count11 & x2);_X007 = EXP( av0 & av1 & !av4 & count11 & x2);_X008 = EXP( av0 & av1 & count11 & !count23 & x2);-- Node name is 'count30' from file "p1024sl.tdf" line 24, column 47-- Equation name is 'count30', location is LC119, type is buried.count30 = TFFE( VCC, countstr, VCC, VCC, VCC);-- Node name is 'count31' from file "p1024sl.tdf" line 24, column 47-- Equation name is 'count31', location is LC124, type is buried.count31 = TFFE( count30, countstr, VCC, VCC, VCC);-- Node name is 'count41' from file "p1024sl.tdf" line 25, column 7-- Equation name is 'count41', location is LC102, type is buried.count41 = TFFE( _EQ031, !av6, !_EQ032, VCC, VCC);_EQ031 = count41 & !count42 & count43# av7;_EQ032 = count41 & !count42 & count43;-- Node name is 'count42' from file "p1024sl.tdf" line 25, column 7-- Equation name is 'count42', location is LC112, type is buried.count42 = TFFE( _EQ033, !av6, !_EQ034, VCC, VCC);_EQ033 = av7 & count41 & !count42 & !count43# av7 & count41 & count42;_EQ034 = count41 & !count42 & count43;-- Node name is 'count43' from file "p1024sl.tdf" line 25, column 7-- Equation name is 'count43', location is LC030, type is buried.count43 = TFFE( _EQ035, !av6, !_EQ036, VCC, VCC);_EQ035 = av7 & count41 & count42 & !count43# av7 & count41 & count43# count41 & !count42 & count43;_EQ036 = count41 & !count42 & count43;-- Node name is 'csos' = 'port7ffd4' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'csos', location is LC046, type is output.csos = DFFE( d4 $ GND, _EQ037, GLOBAL( res), VCC, VCC);_EQ037 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'delay' from file "p1024sl.tdf" line 28, column 1-- Equation name is 'delay', location is LC042, type is buried.delay = DFFE( _EQ038 $ VCC, clk, VCC, VCC, VCC);_EQ038 = delay & !iorq;-- Node name is 'dsp~1' from file "p1024sl.tdf" line 200, column 29-- Equation name is 'dsp~1', location is LC028, type is buried.-- synthesized logic cell_LC028 = LCELL( _EQ039 $ GND);_EQ039 = !av3 & av4 & av6 & av7 & !count23 & count41 & count42# av3 & !av6# av3 & !av7# av3 & !count41# av3 & !count42;-- Node name is 'flash0' from file "p1024sl.tdf" line 27, column 57-- Equation name is 'flash0', location is LC107, type is buried.flash0 = TFFE( VCC, _EQ040, VCC, VCC, VCC);_EQ040 = av6 & av7 & count41 & count42;-- Node name is 'flash1' from file "p1024sl.tdf" line 27, column 57-- Equation name is 'flash1', location is LC099, type is buried.flash1 = TFFE( flash0, _EQ041, VCC, VCC, VCC);_EQ041 = av6 & av7 & count41 & count42;-- Node name is 'flash2' from file "p1024sl.tdf" line 27, column 57-- Equation name is 'flash2', location is LC116, type is buried.flash2 = TFFE( _EQ042, _EQ043, VCC, VCC, VCC);_EQ042 = flash0 & flash1;_EQ043 = av6 & av7 & count41 & count42;-- Node name is 'flash3' from file "p1024sl.tdf" line 27, column 57-- Equation name is 'flash3', location is LC127, type is buried.flash3 = TFFE( _EQ044, _EQ045, VCC, VCC, VCC);_EQ044 = flash0 & flash1 & flash2;_EQ045 = av6 & av7 & count41 & count42;-- Node name is 'flash4' from file "p1024sl.tdf" line 27, column 57-- Equation name is 'flash4', location is LC113, type is buried.flash4 = TFFE( _EQ046, _EQ047, VCC, VCC, VCC);_EQ046 = flash0 & flash1 & flash2 & flash3;_EQ047 = av6 & av7 & count41 & count42;-- Node name is 'g' = 'brgout2' from file "p1024sl.tdf" line 27, column 70-- Equation name is 'g', location is LC125, type is output.g = DFFE( _EQ048 $ VCC, !trig0, !_EQ049, VCC, VCC);_EQ048 = !_LC114 & !_LC121 & !_LC122 & _X027 & _X028 & _X029 & _X030 &_X031;_X027 = EXP( count43 & porteff70 & !porteff74 & portfe2);_X028 = EXP(!bordtrg & !porteff70 & raml2 & raml5);_X029 = EXP(!count23 & porteff70 & !porteff74 & portfe2);_X030 = EXP( portfe2 & raml2 & raml5);_X031 = EXP( bordtrg & portfe2);_EQ049 = !_LC028 & _X015 & _X016 & _X017 & _X018 & _X019 & _X020 &_X021 & _X022;_X015 = EXP(!av6 & count23);_X016 = EXP(!av7 & count23);_X017 = EXP( count23 & !count41);_X018 = EXP( count23 & !count42);_X019 = EXP(!av4 & !av6);_X020 = EXP(!av4 & !av7);_X021 = EXP(!av4 & !count41);_X022 = EXP(!av4 & !count42);-- Node name is 'hl' = 'penttrg1' from file "p1024sl.tdf" line 25, column 42-- Equation name is 'hl', location is LC072, type is output.hl = DFFE( _EQ050 $ GND, cas, rfsh, VCC, VCC);_EQ050 = !hl & !memtrg & !mreq & porteff72# a15 & !hl & !memtrg & !mreq# a14 & !hl & !memtrg & !mreq;-- Node name is 'int' = 'inttrg' from file "p1024sl.tdf" line 25, column 34-- Equation name is 'int', location is LC005, type is output.int = DFFE( GND $ GND, _EQ051, VCC, !_EQ052, VCC);_EQ051 = av6 & av7 & count41 & count42;_EQ052 = !av2 & av3;-- Node name is 'memtrg' from file "p1024sl.tdf" line 26, column 1-- Equation name is 'memtrg', location is LC023, type is buried.memtrg = DFFE( _EQ053 $ porteff74, hl, !_EQ054, VCC, VCC);_EQ053 = count23 & !count42 & !count43 & !porteff74# count23 & !count41 & !count43 & !porteff74;_EQ054 = count11 & x2;-- Node name is 'mem0'-- Equation name is 'mem0', location is LC037, type is output.mem0 = LCELL( _EQ055 $ GND);_EQ055 = a14 & a15 & !porteff71 & port7ffd5;-- Node name is 'mem1'-- Equation name is 'mem1', location is LC040, type is output.mem1 = LCELL( _EQ056 $ hl);_EQ056 = a14 & a15 & hl & port7ffd2# a14 & !a15 & hl;-- Node name is 'mem2'-- Equation name is 'mem2', location is LC043, type is output.mem2 = LCELL( _EQ057 $ GND);_EQ057 = a14 & a15 & !porteff71 & port7ffd6;-- Node name is 'mem3'-- Equation name is 'mem3', location is LC045, type is output.mem3 = LCELL( _EQ058 $ GND);_EQ058 = a14 & a15 & !porteff71 & port7ffd7;-- Node name is 'ob~1' from file "p1024sl.tdf" line 243, column 8-- Equation name is 'ob~1', location is LC098, type is buried.-- synthesized logic cell_LC098 = LCELL( _EQ059 $ GND);_EQ059 = !bordtrg & count23 & !count42 & !count43 & porteff70 & raml0 &trig1# !bordtrg & count23 & !count41 & !count43 & porteff70 & raml0 &trig1# !bordtrg & count23 & !count42 & !count43 & porteff70 & raml3 &!trig1# !bordtrg & count23 & !count41 & !count43 & porteff70 & raml3 &!trig1# !bordtrg & flash4 & !porteff70 & raml3 & raml7 & shift7;-- Node name is 'ob~2' from file "p1024sl.tdf" line 243, column 8-- Equation name is 'ob~2', location is LC100, type is buried.-- synthesized logic cell_LC100 = LCELL( _EQ060 $ GND);_EQ060 = !bordtrg & flash4 & !porteff70 & raml0 & raml7 & !shift7# count41 & count42 & porteff70 & !porteff74 & portfe0# !bordtrg & porteff70 & porteff74 & raml0 & trig1# !bordtrg & porteff70 & porteff74 & raml3 & !trig1# !bordtrg & !flash4 & !porteff70 & raml0 & shift7;-- Node name is 'ob~3' from file "p1024sl.tdf" line 243, column 8-- Equation name is 'ob~3', location is LC105, type is buried.-- synthesized logic cell_LC105 = LCELL( _EQ061 $ GND);_EQ061 = !bordtrg & !porteff70 & raml0 & !raml7 & shift7# !bordtrg & !porteff70 & raml3 & !raml7 & !shift7# !bordtrg & !flash4 & !porteff70 & raml3 & !shift7# porteff70 & portfe0 & raml0 & trig1# porteff70 & portfe0 & raml3 & !trig1;-- Node name is 'og~1' from file "p1024sl.tdf" line 243, column 23-- Equation name is 'og~1', location is LC121, type is buried.-- synthesized logic cell_LC121 = LCELL( _EQ062 $ GND);_EQ062 = !bordtrg & count23 & !count42 & !count43 & porteff70 & raml2 &trig1# !bordtrg & count23 & !count41 & !count43 & porteff70 & raml2 &trig1# !bordtrg & count23 & !count42 & !count43 & porteff70 & raml5 &!trig1# !bordtrg & count23 & !count41 & !count43 & porteff70 & raml5 &!trig1# !bordtrg & flash4 & !porteff70 & raml5 & raml7 & shift7;-- Node name is 'og~2' from file "p1024sl.tdf" line 243, column 23-- Equation name is 'og~2', location is LC122, type is buried.-- synthesized logic cell_LC122 = LCELL( _EQ063 $ GND);_EQ063 = !bordtrg & flash4 & !porteff70 & raml2 & raml7 & !shift7# count41 & count42 & porteff70 & !porteff74 & portfe2# !bordtrg & porteff70 & porteff74 & raml2 & trig1# !bordtrg & porteff70 & porteff74 & raml5 & !trig1# !bordtrg & !flash4 & !porteff70 & raml2 & shift7;-- Node name is 'og~3' from file "p1024sl.tdf" line 243, column 23-- Equation name is 'og~3', location is LC114, type is buried.-- synthesized logic cell_LC114 = LCELL( _EQ064 $ GND);_EQ064 = !bordtrg & !porteff70 & raml2 & !raml7 & shift7# !bordtrg & !porteff70 & raml5 & !raml7 & !shift7# !bordtrg & !flash4 & !porteff70 & raml5 & !shift7# porteff70 & portfe2 & raml2 & trig1# porteff70 & portfe2 & raml5 & !trig1;-- Node name is 'orr~1' from file "p1024sl.tdf" line 243, column 16-- Equation name is 'orr~1', location is LC093, type is buried.-- synthesized logic cell_LC093 = LCELL( _EQ065 $ GND);_EQ065 = !bordtrg & count23 & !count42 & !count43 & porteff70 & raml1 &trig1# !bordtrg & count23 & !count41 & !count43 & porteff70 & raml1 &trig1# !bordtrg & count23 & !count42 & !count43 & porteff70 & raml4 &!trig1# !bordtrg & count23 & !count41 & !count43 & porteff70 & raml4 &!trig1# !bordtrg & flash4 & !porteff70 & raml4 & raml7 & shift7;-- Node name is 'orr~2' from file "p1024sl.tdf" line 243, column 16-- Equation name is 'orr~2', location is LC094, type is buried.-- synthesized logic cell_LC094 = LCELL( _EQ066 $ GND);_EQ066 = !bordtrg & flash4 & !porteff70 & raml1 & raml7 & !shift7# count41 & count42 & porteff70 & !porteff74 & portfe1# !bordtrg & porteff70 & porteff74 & raml1 & trig1# !bordtrg & porteff70 & porteff74 & raml4 & !trig1# !bordtrg & !flash4 & !porteff70 & raml1 & shift7;-- Node name is 'orr~3' from file "p1024sl.tdf" line 243, column 16-- Equation name is 'orr~3', location is LC084, type is buried.-- synthesized logic cell_LC084 = LCELL( _EQ067 $ GND);_EQ067 = !bordtrg & !porteff70 & raml1 & !raml7 & shift7# !bordtrg & !porteff70 & raml4 & !raml7 & !shift7# !bordtrg & !flash4 & !porteff70 & raml4 & !shift7# porteff70 & portfe1 & raml1 & trig1# porteff70 & portfe1 & raml4 & !trig1;-- Node name is 'penttrg2' from file "p1024sl.tdf" line 25, column 52-- Equation name is 'penttrg2', location is LC044, type is buried.penttrg2 = TFFE(!hl, cas, VCC, VCC, VCC);-- Node name is 'porteff70' from file "p1024sl.tdf" line 26, column 17-- Equation name is 'porteff70', location is LC004, type is buried.porteff70 = DFFE( d0 $ GND, _EQ068, GLOBAL( res), VCC, VCC);_EQ068 = !clk & !iorq & !port1 & !port2;-- Node name is 'porteff71' from file "p1024sl.tdf" line 26, column 17-- Equation name is 'porteff71', location is LC002, type is buried.porteff71 = DFFE( d2 $ GND, _EQ069, GLOBAL( res), VCC, VCC);_EQ069 = !clk & !iorq & !port1 & !port2;-- Node name is 'porteff72' from file "p1024sl.tdf" line 26, column 17-- Equation name is 'porteff72', location is LC013, type is buried.porteff72 = DFFE( d3 $ GND, _EQ070, GLOBAL( res), VCC, VCC);_EQ070 = !clk & !iorq & !port1 & !port2;-- Node name is 'porteff73' from file "p1024sl.tdf" line 26, column 17-- Equation name is 'porteff73', location is LC034, type is buried.porteff73 = DFFE( d4 $ GND, _EQ071, GLOBAL( res), VCC, VCC);_EQ071 = !clk & !iorq & !port1 & !port2;-- Node name is 'porteff74' from file "p1024sl.tdf" line 26, column 17-- Equation name is 'porteff74', location is LC007, type is buried.porteff74 = DFFE( d6 $ GND, _EQ072, GLOBAL( res), VCC, VCC);_EQ072 = !clk & !iorq & !port1 & !port2;-- Node name is 'portfe0' from file "p1024sl.tdf" line 27, column 44-- Equation name is 'portfe0', location is LC012, type is buried.portfe0 = DFFE( d0 $ GND, _EQ073, VCC, VCC, VCC);_EQ073 = !port1 & port2;-- Node name is 'portfe1' from file "p1024sl.tdf" line 27, column 44-- Equation name is 'portfe1', location is LC011, type is buried.portfe1 = DFFE( d1 $ GND, _EQ074, VCC, VCC, VCC);_EQ074 = !port1 & port2;-- Node name is 'portfe2' from file "p1024sl.tdf" line 27, column 44-- Equation name is 'portfe2', location is LC015, type is buried.portfe2 = DFFE( d2 $ GND, _EQ075, VCC, VCC, VCC);_EQ075 = !port1 & port2;-- Node name is 'port7ffd0' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'port7ffd0', location is LC001, type is buried.port7ffd0 = DFFE( d0 $ GND, _EQ076, GLOBAL( res), VCC, VCC);_EQ076 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'port7ffd1' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'port7ffd1', location is LC009, type is buried.port7ffd1 = DFFE( d1 $ GND, _EQ077, GLOBAL( res), VCC, VCC);_EQ077 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'port7ffd2' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'port7ffd2', location is LC010, type is buried.port7ffd2 = DFFE( d2 $ GND, _EQ078, GLOBAL( res), VCC, VCC);_EQ078 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'port7ffd5' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'port7ffd5', location is LC036, type is buried.port7ffd5 = DFFE( d5 $ GND, _EQ079, GLOBAL( res), VCC, VCC);_EQ079 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'port7ffd6' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'port7ffd6', location is LC008, type is buried.port7ffd6 = DFFE( d6 $ GND, _EQ080, GLOBAL( res), VCC, VCC);_EQ080 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'port7ffd7' from file "p1024sl.tdf" line 26, column 33-- Equation name is 'port7ffd7', location is LC041, type is buried.port7ffd7 = DFFE( d7 $ GND, _EQ081, GLOBAL( res), VCC, VCC);_EQ081 = !clk & !iorq & port1 & port2 & _X009;_X009 = EXP( porteff71 & port7ffd5);-- Node name is 'r' = 'brgout1' from file "p1024sl.tdf" line 27, column 70-- Equation name is 'r', location is LC085, type is output.r = DFFE( _EQ082 $ VCC, !trig0, !_EQ083, VCC, VCC);_EQ082 = !_LC084 & !_LC093 & !_LC094 & _X032 & _X033 & _X034 & _X035 &_X036;_X032 = EXP( count43 & porteff70 & !porteff74 & portfe1);_X033 = EXP(!bordtrg & !porteff70 & raml1 & raml4);_X034 = EXP(!count23 & porteff70 & !porteff74 & portfe1);_X035 = EXP( portfe1 & raml1 & raml4);_X036 = EXP( bordtrg & portfe1);_EQ083 = !_LC028 & _X015 & _X016 & _X017 & _X018 & _X019 & _X020 &_X021 & _X022;_X015 = EXP(!av6 & count23);_X016 = EXP(!av7 & count23);_X017 = EXP( count23 & !count41);_X018 = EXP( count23 & !count42);_X019 = EXP(!av4 & !av6);_X020 = EXP(!av4 & !av7);_X021 = EXP(!av4 & !count41);_X022 = EXP(!av4 & !count42);-- Node name is 'raml0' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml0', location is LC018, type is buried.raml0 = DFFE( ramo0 $ GND, _EQ084, VCC, VCC, VCC);_EQ084 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'raml1' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml1', location is LC031, type is buried.raml1 = DFFE( ramo1 $ GND, _EQ085, VCC, VCC, VCC);_EQ085 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'raml2' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml2', location is LC029, type is buried.raml2 = DFFE( ramo2 $ GND, _EQ086, VCC, VCC, VCC);_EQ086 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'raml3' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml3', location is LC019, type is buried.raml3 = DFFE( ramo3 $ GND, _EQ087, VCC, VCC, VCC);_EQ087 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'raml4' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml4', location is LC032, type is buried.raml4 = DFFE( ramo4 $ GND, _EQ088, VCC, VCC, VCC);_EQ088 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'raml5' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml5', location is LC051, type is buried.raml5 = DFFE( ramo5 $ GND, _EQ089, VCC, VCC, VCC);_EQ089 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'raml6' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml6', location is LC061, type is buried.raml6 = DFFE( ramo6 $ GND, _EQ090, VCC, VCC, VCC);_EQ090 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'raml7' from file "p1024sl.tdf" line 27, column 17-- Equation name is 'raml7', location is LC059, type is buried.raml7 = DFFE( ramo7 $ GND, _EQ091, VCC, VCC, VCC);_EQ091 = _X037 & _X038;_X037 = EXP( count11 & !porteff70);_X038 = EXP( porteff70 & !trig1);-- Node name is 'ramo0' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo0', location is LC058, type is buried.ramo0 = DFFE( ram0 $ GND, _EQ092, VCC, VCC, VCC);_EQ092 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramo1' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo1', location is LC048, type is buried.ramo1 = DFFE( ram1 $ GND, _EQ093, VCC, VCC, VCC);_EQ093 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramo2' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo2', location is LC057, type is buried.ramo2 = DFFE( ram2 $ GND, _EQ094, VCC, VCC, VCC);_EQ094 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramo3' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo3', location is LC055, type is buried.ramo3 = DFFE( ram3 $ GND, _EQ095, VCC, VCC, VCC);_EQ095 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramo4' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo4', location is LC050, type is buried.ramo4 = DFFE( ram4 $ GND, _EQ096, VCC, VCC, VCC);_EQ096 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramo5' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo5', location is LC060, type is buried.ramo5 = DFFE( ram5 $ GND, _EQ097, VCC, VCC, VCC);_EQ097 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramo6' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo6', location is LC056, type is buried.ramo6 = DFFE( ram6 $ GND, _EQ098, VCC, VCC, VCC);_EQ098 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramo7' from file "p1024sl.tdf" line 27, column 5-- Equation name is 'ramo7', location is LC054, type is buried.ramo7 = DFFE( ram7 $ GND, _EQ099, VCC, VCC, VCC);_EQ099 = _X039 & _X040;_X039 = EXP( porteff70 & ras);_X040 = EXP(!hl & penttrg2 & !porteff70 & !ras);-- Node name is 'ramq0' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq0', location is LC033, type is buried.ramq0 = DFFE( ram0 $ GND, _EQ100, VCC, VCC, VCC);_EQ100 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ramq1' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq1', location is LC047, type is buried.ramq1 = DFFE( ram1 $ GND, _EQ101, VCC, VCC, VCC);_EQ101 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ramq2' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq2', location is LC064, type is buried.ramq2 = DFFE( ram2 $ GND, _EQ102, VCC, VCC, VCC);_EQ102 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ramq3' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq3', location is LC052, type is buried.ramq3 = DFFE( ram3 $ GND, _EQ103, VCC, VCC, VCC);_EQ103 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ramq4' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq4', location is LC049, type is buried.ramq4 = DFFE( ram4 $ GND, _EQ104, VCC, VCC, VCC);_EQ104 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ramq5' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq5', location is LC063, type is buried.ramq5 = DFFE( ram5 $ GND, _EQ105, VCC, VCC, VCC);_EQ105 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ramq6' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq6', location is LC062, type is buried.ramq6 = DFFE( ram6 $ GND, _EQ106, VCC, VCC, VCC);_EQ106 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ramq7' from file "p1024sl.tdf" line 26, column 45-- Equation name is 'ramq7', location is LC053, type is buried.ramq7 = DFFE( ram7 $ GND, _EQ107, VCC, VCC, VCC);_EQ107 = _X041 & _X042;_X041 = EXP(!hl & !penttrg2 & !ras);_X042 = EXP(!hl & porteff70 & !ras);-- Node name is 'ras' = 'trig2' from file "p1024sl.tdf" line 24, column 5-- Equation name is 'ras', location is LC073, type is output.ras = trig2~NOT;trig2~NOT = DFFE(!trig1 $ VCC, GLOBAL(!f14), VCC, VCC, VCC);-- Node name is 'shift0' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift0', location is LC081, type is buried.shift0 = DFFE( _EQ108 $ GND, !trig0, VCC, VCC, VCC);_EQ108 = count11 & ramq0 & !trig1 & x2;-- Node name is 'shift1' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift1', location is LC082, type is buried.shift1 = DFFE( _EQ109 $ shift0, !trig0, VCC, VCC, VCC);_EQ109 = count11 & ramq1 & !shift0 & !trig1 & x2# count11 & !ramq1 & shift0 & !trig1 & x2;-- Node name is 'shift2' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift2', location is LC092, type is buried.shift2 = DFFE( _EQ110 $ shift1, !trig0, VCC, VCC, VCC);_EQ110 = count11 & ramq2 & !shift1 & !trig1 & x2# count11 & !ramq2 & shift1 & !trig1 & x2;-- Node name is 'shift3' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift3', location is LC108, type is buried.shift3 = DFFE( _EQ111 $ shift2, !trig0, VCC, VCC, VCC);_EQ111 = count11 & ramq3 & !shift2 & !trig1 & x2# count11 & !ramq3 & shift2 & !trig1 & x2;-- Node name is 'shift4' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift4', location is LC089, type is buried.shift4 = DFFE( _EQ112 $ shift3, !trig0, VCC, VCC, VCC);_EQ112 = count11 & ramq4 & !shift3 & !trig1 & x2# count11 & !ramq4 & shift3 & !trig1 & x2;-- Node name is 'shift5' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift5', location is LC020, type is buried.shift5 = DFFE( _EQ113 $ shift4, !trig0, VCC, VCC, VCC);_EQ113 = count11 & ramq5 & !shift4 & !trig1 & x2# count11 & !ramq5 & shift4 & !trig1 & x2;-- Node name is 'shift6' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift6', location is LC106, type is buried.shift6 = DFFE( _EQ114 $ shift5, !trig0, VCC, VCC, VCC);_EQ114 = count11 & ramq6 & !shift5 & !trig1 & x2# count11 & !ramq6 & shift5 & !trig1 & x2;-- Node name is 'shift7' from file "p1024sl.tdf" line 27, column 30-- Equation name is 'shift7', location is LC022, type is buried.shift7 = DFFE( _EQ115 $ shift6, !trig0, VCC, VCC, VCC);_EQ115 = count11 & ramq7 & !shift6 & !trig1 & x2# count11 & !ramq7 & shift6 & !trig1 & x2;-- Node name is 'sync'-- Equation name is 'sync', location is LC080, type is output.sync = LCELL( _EQ116 $ _EQ117);_EQ116 = av2# av3# count23;_EQ117 = av6 & av7 & count41 & count42;-- Node name is 'trig0' from file "p1024sl.tdf" line 24, column 5-- Equation name is 'trig0', location is LC096, type is buried.trig0 = TFFE( VCC, GLOBAL( f14), VCC, VCC, VCC);-- Node name is 'trig1' from file "p1024sl.tdf" line 24, column 5-- Equation name is 'trig1', location is LC111, type is buried.trig1 = TFFE( VCC, !trig0, VCC, VCC, VCC);-- Node name is 'trig4' from file "p1024sl.tdf" line 24, column 5-- Equation name is 'trig4', location is LC097, type is buried.trig4 = DFFE( _EQ118 $ porteff73, trig0, VCC, VCC, VCC);_EQ118 = dos & !porteff73 & !rfsh;-- Node name is 'trig5' from file "p1024sl.tdf" line 24, column 5-- Equation name is 'trig5', location is LC039, type is buried.trig5 = DFFE( rfsh $ GND, _EQ119, !_EQ120, VCC, VCC);_EQ119 = !mreq & _X043;_X043 = EXP(!a14 & !a15 & !porteff72);_EQ120 = _X044 & _X045;_X044 = EXP( cas & res);_X045 = EXP(!hl & res);-- Node name is 'wait'-- Equation name is 'wait', location is LC038, type is output.wait = LCELL( _EQ121 $ trig4);_EQ121 = delay & !trig4 & !trig5;-- Node name is 'we'-- Equation name is 'we', location is LC069, type is output.we = LCELL( _EQ122 $ VCC);_EQ122 = hl & !mreq & porteff72 & rd# a15 & hl & !mreq & rd# a14 & hl & !mreq & rd;-- Node name is 'x2' = 'count10' from file "p1024sl.tdf" line 24, column 19-- Equation name is 'x2', location is LC067, type is output.x2 = TFFE( VCC, trig1, VCC, VCC, VCC);-- Node name is 'y0'-- Equation name is 'y0', location is LC027, type is output.y0 = LCELL( _EQ123 $ a14);_EQ123 = a14 & a15 & !port7ffd0;-- Node name is 'y1'-- Equation name is 'y1', location is LC035, type is output.y1 = LCELL( _EQ124 $ a15);_EQ124 = a14 & a15 & !port7ffd1;-- Shareable expanders that are duplicated in multiple LABs:-- _X009 occurs in LABs A, C-- _X015 occurs in LABs A, E, F, H-- _X016 occurs in LABs A, E, F, H-- _X017 occurs in LABs A, E, F, H-- _X018 occurs in LABs A, E, F, H-- _X019 occurs in LABs A, E, F, H-- _X020 occurs in LABs A, E, F, H-- _X021 occurs in LABs A, E, F, H-- _X022 occurs in LABs A, E, F, H-- _X037 occurs in LABs B, D-- _X038 occurs in LABs B, D-- _X039 occurs in LABs C, D-- _X040 occurs in LABs C, D-- _X041 occurs in LABs C, D-- _X042 occurs in LABs C, DProject Information c:\final\p1024sl.rpt** COMPILATION SETTINGS & TIMES **Processing Menu Commands------------------------Design Doctor = offLogic Synthesis:Synthesis Type Used = StandardDefault Synthesis Style = NORMALLogic option settings in 'NORMAL' style for 'MAX7000S' familyDECOMPOSE_GATES = onDUPLICATE_LOGIC_EXTRACTION = onMINIMIZATION = fullMULTI_LEVEL_FACTORING = onNOT_GATE_PUSH_BACK = onPARALLEL_EXPANDERS = offREDUCE_LOGIC = onREFACTORIZATION = onREGISTER_OPTIMIZATION = onRESYNTHESIZE_NETWORK = onSLOW_SLEW_RATE = offSOFT_BUFFER_INSERTION = onSUBFACTOR_EXTRACTION = onTURBO_BIT = onXOR_SYNTHESIS = onIGNORE_SOFT_BUFFERS = offUSE_LPM_FOR_AHDL_OPERATORS = offOther logic synthesis settings:Automatic Global Clock = onAutomatic Global Clear = onAutomatic Global Preset = onAutomatic Global Output Enable = onAutomatic Fast I/O = offAutomatic Register Packing = offAutomatic Open-Drain Pins = onAutomatic Implement in EAB = offOne-Hot State Machine Encoding = offOptimize = 5Default Timing Specifications: NoneCut All Bidir Feedback Timing Paths = onCut All Clear & Preset Timing Paths = onIgnore Timing Assignments = offFunctional SNF Extractor = offLinked SNF Extractor = offTiming SNF Extractor = onOptimize Timing SNF = offGenerate AHDL TDO File = offFitter Settings = NORMALSmart Recompile = offTotal Recompile = offInterfaces Menu Commands------------------------EDIF Netlist Writer = offVerilog Netlist Writer = offVHDL Netlist Writer = offCompilation Times-----------------Compiler Netlist Extractor 00:00:00Database Builder 00:00:00Logic Synthesizer 00:00:00Partitioner 00:00:00Fitter 00:00:01Timing SNF Extractor 00:00:00Assembler 00:00:02-------------------------- --------Total Time 00:00:03Memory Allocated-----------------Peak memory allocated during compilation = 5,519K