Subversion Repositories pentevo

                ifndef  __regtnx4inc
__regtnx4inc    equ     1
                save
                listing off   ; no listing over this file

;****************************************************************************
;*                                                                          *
;*   AS 1.42 - File REGTNX4.INC                                             *
;*                                                                          *
;*   Contains Common Bit & Register Definitions for ATtiny24(A)/44(A)/84(A) *
;*                                                                          *
;****************************************************************************

;----------------------------------------------------------------------------
; Chip Configuration

MCUCR           port    0x35            ; MCU General Control Register
BODSE           avrbit  MCUCR,2         ; BOD Sleep
SM0             avrbit  MCUCR,3         ; Sleep Mode Select
SM1             avrbit  MCUCR,4
SE              avrbit  MCUCR,5         ; Sleep Enable
BODS            avrbit  MCUCR,7         ; BOD Sleep Enable

MCUSR           port    0x34            ; MCU Status Register
WDRF            avrbit  MCUSR,3         ; Watchdog Reset Flag
BORF            avrbit  MCUSR,2         ; Brown-out Reset Flag
EXTRF           avrbit  MCUSR,1         ; External Reset Flag
PORF            avrbit  MCUSR,0         ; Power-On Reset Flag

OSCCAL          port    0x31            ; Oscillator Calibration

CLKPR           port    0x26            ; Clock Prescaler
CLKPS0          avrbit  CLKPR,0         ; Prescaler Select
CLKPS1          avrbit  CLKPR,1
CLKPS2          avrbit  CLKPR,2
CLKPS3          avrbit  CLKPR,3
CLKPCE          avrbit  CLKPR,7         ; Clock Prescaler Change Enable

PRR             port    0x00            ; Power Reduction Register
PRADC           avrbit  PRR,0           ; Power Reduction AD Converter
PRUSI           avrbit  PRR,1           ; Power Reduction USI
PRTIM0          avrbit  PRR,2           ; Power Reduction Timer/Counter 0
PRTIM1          avrbit  PRR,3           ; Power Reduction Timer/Counter 1

;----------------------------------------------------------------------------
; EEPROM/Flash Access

EEARL           port    0x1e            ; EEPROM Address Register Low
EEARH           port    0x1f            ; EEPROM Address Register High
EEDR            port    0x1d            ; EEPROM Data Register
EECR            port    0x1c            ; EEPROM Control Register
EEPM1           avrbit  EECR,5          ; EEPROM Program Mode
EEPM0           avrbit  EECR,4
EERIE           avrbit  EECR,3          ; EEPROM Ready Interrupt Enable
EEMPE           avrbit  EECR,2          ; EEPROM Master Write Enable
EEPE            avrbit  EECR,1          ; EEPROM Write Enable
EERE            avrbit  EECR,0          ; EEPROM Read Enable

SPMCSR          port    0x37            ; Store Program Memory Control/Status Register
CTPB            avrbit  SPMCSR,4        ; Clear Temporary Page Buffer
RFLB            avrbit  SPMCSR,3        ; Read Fuse and Lock Bits
PGWRT           avrbit  SPMCSR,2        ; Page Write
PGERS           avrbit  SPMCSR,1        ; Page Erase
SPMEN           avrbit  SPMCSR,0        ; Self Programming Enable

;----------------------------------------------------------------------------
; JTAG etc.

DWDR            port    0x27            ; debugWire Data Register

;----------------------------------------------------------------------------
; GPIO

PUD             avrbit  MCUCR,6         ; Pull-Up Disable

PINA            port    0x19            ; Port A @ 0x19 (IO) ff.
PINB            port    0x16            ; Port B @ 0x16 (IO) ff. (bit 0..3)

GPIOR0          port    0x13            ; General Purpose I/O Register 0
GPIOR1          port    0x14            ; General Purpose I/O Register 1
GPIOR2          port    0x15            ; General Purpose I/O Register 2

DIDR0           port    0x01            ; Digital Input Disable Register 0
ADC0D           avrbit  DIDR0,0         ; ADC0 Digital Input Disable
ADC1D           avrbit  DIDR0,1         ; ADC1 Digital Input Disable
ADC2D           avrbit  DIDR0,2         ; ADC2 Digital Input Disable
ADC3D           avrbit  DIDR0,3         ; ADC3 Digital Input Disable
ADC4D           avrbit  DIDR0,4         ; ADC4 Digital Input Disable
ADC5D           avrbit  DIDR0,5         ; ADC5 Digital Input Disable
ADC6D           avrbit  DIDR0,6         ; ADC6 Digital Input Disable
ADC7D           avrbit  DIDR0,7         ; ADC7 Digital Input Disable

PCMSK0          port    0x12            ; Pin Change Interrupt Mask 0
PCMSK1          port    0x20            ; Pin Change Interrupt Mask 1
PCINT8          avrbit  PCMSK1,0        ; Enable Pin Change Interrupt 8
PCINT9          avrbit  PCMSK1,1        ; Enable Pin Change Interrupt 9
PCINT10         avrbit  PCMSK1,2        ; Enable Pin Change Interrupt 10
PCINT11         avrbit  PCMSK1,3        ; Enable Pin Change Interrupt 11

;----------------------------------------------------------------------------
; Interrupt Vectors

                enumconf 1,code
                enum     INT0_vect=1            ; External Interrupt Request 0
                nextenum PCINT0_vect            ; Pin Change Interrupt 0
                nextenum PCINT1_vect            ; Pin Change Interrupt 1
                nextenum WDT_vect               ; Watchdog Time-Out
                nextenum TIMER1_CAPT_vect       ; Timer/Counter 1 Capture Event
                nextenum TIMER1_COMPA_vect      ; Timer/Counter 1 Compare Match A
                nextenum TIMER1_COMPB_vect      ; Timer/Counter 1 Compare Match B
                nextenum TIMER1_OVF_vect        ; Timer/Counter 1 Overflow
                nextenum TIMER0_COMPA_vect      ; Timer/Counter 0 Compare Match A
                nextenum TIMER0_COMPB_vect      ; Timer/Counter 0 Compare Match B
                nextenum TIMER0_OVF_vect        ; Timer/Counter 0 Overflow
                nextenum ANA_COMP_vect          ; Analog Comparator
                nextenum ADC_vect               ; ADC Conversion Complete
                nextenum EE_RDY_vect            ; EEPROM Ready
                nextenum USI_START_vect         ; USI Start
                nextenum USI_OVF_vect           ; USI Overflow

;----------------------------------------------------------------------------
; External Interrupts

ISC00           avrbit  MCUCR,0         ; External Interrupt 0 Sense Control
ISC01           avrbit  MCUCR,1

GIMSK           port    0x3b            ; General Interrupt Mask Register
INT0            avrbit  GIMSK,6         ; Enable External Interrupt 0
PCIE1           avrbit  GIMSK,5         ; Pin Change Interrupt Enable 1
PCIE0           avrbit  GIMSK,4         ; Pin Change Interrupt Enable 0

GIFR            port    0x3a            ; General Interrupt Flag Register
INTF0           avrbit  GIFR,6          ; External Interrupt 0 Occured
PCIF1           avrbit  GIFR,5          ; Pin Change Interrupt 1 Occured
PCIF0           avrbit  GIFR,4          ; Pin Change Interrupt 0 Occured

;----------------------------------------------------------------------------
; Timers

TCCR0A          port    0x30            ; Timer/Counter 0 Control Register A
WGM00           avrbit  TCCR0A,0        ; Timer/Counter 0 Waveform Generation Mode
WGM01           avrbit  TCCR0A,1
COM0B0          avrbit  TCCR0A,4        ; Timer/Counter 0 Output Compare Mode B
COM0B1          avrbit  TCCR0A,5
COM0A0          avrbit  TCCR0A,6        ; Timer/Counter 0 Output Compare Mode A
COM0A1          avrbit  TCCR0A,7
TCCR0B          port    0x33            ; Timer/Counter 0 Control Register B
CS00            avrbit  TCCR0B,0        ; Timer/Counter 0 Clock Select
CS01            avrbit  TCCR0B,1
CS02            avrbit  TCCR0B,2
WGM02           avrbit  TCCR0B,3
FOC0B           avrbit  TCCR0B,6        ; Timer/Counter 0 Force Output Compare B
FOC0A           avrbit  TCCR0B,7        ; Timer/Counter 0 Force Output Compare A
TCNT0           port    0x32            ; Timer/Counter 0 Value
OCR0A           port    0x36            ; Timer/Counter 0 Output Compare Value A
OCR0B           port    0x3c            ; Timer/Counter 0 Output Compare Value B

TCCR1A          port    0x2f            ; Timer/Counter 1 Control Register A
WGM10           avrbit  TCCR1A,0        ; Timer/Counter 1 Waveform Generation Mode
WGM11           avrbit  TCCR1A,1
COM1B0          avrbit  TCCR1A,4        ; Timer/Counter 1 Output Compare Mode B
COM1B1          avrbit  TCCR1A,5
COM1A0          avrbit  TCCR1A,6        ; Timer/Counter 1 Output Compare Mode A
COM1A1          avrbit  TCCR1A,7
TCCR1B          port    0x2e            ; Timer/Counter 1 Control Register B
CS10            avrbit  TCCR1B,0        ; Timer/Counter 1 Clock Select
CS11            avrbit  TCCR1B,1
CS12            avrbit  TCCR1B,2
WGM12           avrbit  TCCR1B,3
WGM13           avrbit  TCCR1B,4
ICES1           avrbit  TCCR1B,6        ; Timer/Counter 1 Input Capture Edge Select
ICNC1           avrbit  TCCR1B,7        ; Timer/Counter 1 Input Capture Noise Canceling
TCCR1C          port    0x22            ; Timer/Counter 1 Control Register C
FOC1B           avrbit  TCCR1C,6        ; Timer/Counter 1 Force Output Compare B
FOC1A           avrbit  TCCR1C,7        ; Timer/Counter 1 Force Output Compare A
TCNT1L          port    0x2c            ; Timer/Counter 1 Value LSB
TCNT1H          port    0x2d            ; Timer/Counter 1 Value MSB
OCR1AL          port    0x2a            ; Timer/Counter 1 Output Compare Value A LSB
OCR1AH          port    0x2b            ; Timer/Counter 1 Output Compare Value A MSB
OCR1BL          port    0x28            ; Timer/Counter 1 Output Compare Value B LSB
OCR1BH          port    0x29            ; Timer/Counter 1 Output Compare Value B MSB
ICR1L           port    0x24            ; Timer/Counter 1 Input Capture Value LSB
ICR1H           port    0x25            ; Timer/Counter 1 Input Capture Value MSB

TIMSK0          port    0x39            ; Timer/Counter Interrupt Mask Register 0
TOIE0           avrbit  TIMSK0,0        ; Timer/Counter 0 Overflow Interrupt Enable
OCIE0A          avrbit  TIMSK0,1        ; Timer/Counter 0 Output Compare Interrupt Enable A
OCIE0B          avrbit  TIMSK0,2        ; Timer/Counter 0 Output Compare Interrupt Enable B

TIMSK1          port    0x0c            ; Timer/Counter Interrupt Mask Register 1
TOIE1           avrbit  TIMSK1,0        ; Timer/Counter 1 Overflow Interrupt Enable
OCIE1A          avrbit  TIMSK1,1        ; Timer/Counter 1 Output Compare Interrupt Enable A
OCIE1B          avrbit  TIMSK1,2        ; Timer/Counter 1 Output Compare Interrupt Enable B
ICIE1           avrbit  TIMSK1,5        ; Timer/Counter 1 Input Capture Interrupt Enable

TIFR0           port    0x38            ; Timer Interrupt Status Register 0
TIFR1           port    0x0b            ; Timer Interrupt Status Register 1

GTCCR           port    0x23            ; General Timer/Counter Control 1 Register
PSR10           avrbit  GTCCR,0         ; Prescaler Reset Timer/Counter 0/1
TSM             avrbit  GTCCR,7         ; Timer/Counter Synchronization Mode

;----------------------------------------------------------------------------
; Watchdog Timer

                include "wdm21.inc"

WDCE            avrbit  WDTCR,4         ; Change Enable
WDP3            avrbit  WDTCR,5
WDIE            avrbit  WDTCR,6         ; Enable Watchdog Interrupt
WDIF            avrbit  WDTCR,7         ; Watchdog Interrupt Occured?

;----------------------------------------------------------------------------
; Analog Comparator

                include "acm.inc"

;----------------------------------------------------------------------------
; A/D Converter

ADMUX           port    0x07            ; Multiplexer Selection
REFS1           avrbit  ADMUX,7         ; Reference Selection Bits
REFS0           avrbit  ADMUX,6
MUX5            avrbit  ADMUX,5         ; Multiplexer
MUX4            avrbit  ADMUX,4
MUX3            avrbit  ADMUX,3
MUX2            avrbit  ADMUX,2
MUX1            avrbit  ADMUX,1
MUX0            avrbit  ADMUX,0

ADCSRA          port    0x06            ; Control/Status Register A
ADEN            avrbit  ADCSRA,7        ; Enable ADC
ADSC            avrbit  ADCSRA,6        ; Start Conversion
ADATE           avrbit  ADCSRA,5        ; ADC Auto Trigger Enable
ADIF            avrbit  ADCSRA,4        ; Interrupt Flag
ADIE            avrbit  ADCSRA,3        ; Interrupt Enable
ADPS2           avrbit  ADCSRA,2        ; Prescaler Select
ADPS1           avrbit  ADCSRA,1
ADPS0           avrbit  ADCSRA,0

ADCSRB          port    0x03            ; Control/Status Register B
BIN             avrbit  ADCSRB,7        ; Bipolar Input Mode
ACME            avrbit  ADCSRB,6        ; Analog Comparator Multiplexer Enable
ADLAR           avrbit  ADCSRB,4        ; Left Adjust Right
ADTS2           avrbit  ADCSRB,2        ; Auto Trigger Source
ADTS1           avrbit  ADCSRB,1
ADTS0           avrbit  ADCSRB,0

ADCH            port    0x05            ; Data Register
ADCL            port    0x04

;----------------------------------------------------------------------------
; USI

USIDR           port    0x0f            ; USI Data Register

USISR           port    0x0e            ; USI Status Register
USICNT0         avrbit  USISR,0         ; Counter Value
USICNT1         avrbit  USISR,1
USICNT2         avrbit  USISR,2
USICNT3         avrbit  USISR,3
USIDC           avrbit  USISR,4         ; Data Output Collision
USIPF           avrbit  USISR,5         ; Stop Condition Flag
USIOIF          avrbit  USISR,6         ; Counter Overflow Interrupt Flag
USISIF          avrbit  USISR,7         ; Start Condition Interrupt Flag

USICR           port    0x0d            ; USI Control Register
USITC           avrbit  USICR,0         ; Toggle Clock Port Pin
USICLK          avrbit  USICR,1         ; Clock Strobe
USICS0          avrbit  USICR,2         ; Clock Source Select
USICS1          avrbit  USICR,3
USIWM0          avrbit  USICR,4         ; Wire Mode
USIWM1          avrbit  USICR,5         
USIOIE          avrbit  USICR,6         ; Counter Overflow Interrupt Enable
USISIE          avrbit  USICR,7         ; Start Condition Interrupt Enable

USIBR           port    0x10            ; USI Buffer Register

                restore                 ; re-enable listing

                endif                   ; __regtnx4inc