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ifndef __tr24inc__tr24inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File TR24.INC *;* *;* Contains Bit & Register Definitions for ATmega RFR2 Transceiver *;* *;****************************************************************************AES_CTRL sfr 0x13c ; AES Control RegisterAES_REQUEST avrbit AES_CTRL,7 ; Request AES OperationAES_MODE avrbit AES_CTRL,5 ; Set AES Operation ModeAES_DIR avrbit AES_CTRL,3 ; Set AES Operation DirectionAES_IM avrbit AES_CTRL,2 ; AES Interrupt EnableAES_STATUS sfr 0x13d ; AES Status RegisterAES_ER avrbit AES_STATUS,7 ; AES Operation Finished with ErrorAES_DONE avrbit AES_STATUS,0 ; AES Operation Finished with SuccessAES_STATE sfr 0x13e ; AES Plain and Cipher Text Buffer RegisterAES_KEY sfr 0x13f ; AES Encryption and Decryption Key Buffer RegisterTRX_STATUS sfr 0x141 ; Transceiver Status RegisterCCA_DONE avrbit TRX_STATUS,7 ; CCA Algorithm StatusCCA_STATUS avrbit TRX_STATUS,6 ; CCA Status ResultTST_STATUS avrbit TRX_STATUS,5 ; Test Mode StatusTRX_STATUS4 avrbit TRX_STATUS,4 ; Transceiver Main StatusTRX_STATUS3 avrbit TRX_STATUS,3TRX_STATUS2 avrbit TRX_STATUS,2TRX_STATUS1 avrbit TRX_STATUS,1TRX_STATUS0 avrbit TRX_STATUS,0TRX_STATE sfr 0x142 ; Transceiver State Control RegisterTRAC_STATUS2 avrbit TRX_STATE,7 ; Transaction StatusTRAC_STATUS1 avrbit TRX_STATE,6TRAC_STATUS0 avrbit TRX_STATE,5TRX_CMD4 avrbit TRX_STATE,4 ; State Control CommandTRX_CMD3 avrbit TRX_STATE,3TRX_CMD2 avrbit TRX_STATE,2TRX_CMD1 avrbit TRX_STATE,1TRX_CMD0 avrbit TRX_STATE,0TRX_CTRL_0 sfr 0x143 ; ReservedTRX_CTRL_1 sfr 0x144 ; Transceiver Control Register 1PA_EXT_EN avrbit TRX_CTRL_1,7 ; External PA Support EnableIRQ_2_EXT_EN avrbit TRX_CTRL_1,6 ; Connect Frame Start IRQ to TC1TX_AUTO_CRC_ON avrbit TRX_CTRL_1,5 ; Enable Automatic CRC CalculationPLL_TX_FLT avrbit TRX_CTRL_1,4 ; Enable PLL TX FilterPHY_TX_PWR sfr 0x145 ; Transceiver Transmit Power Control RegisterTX_PWR3 avrbit PHY_TX_PWR,3 ; Transmit Power SettingTX_PWR2 avrbit PHY_TX_PWR,2TX_PWR1 avrbit PHY_TX_PWR,1TX_PWR0 avrbit PHY_TX_PWR,0PARCR sfr 0x138 ; Power Amplifier Ramp Up/Down Control RegisterPALTD2 avrbit PARCR,7 ; ext. PA Ramp Down Lead TimePALTD1 avrbit PARCR,6PALTD0 avrbit PARCR,5PALTU2 avrbit PARCR,4 ; ext. PA Ramp Up Lead TimePALTU1 avrbit PARCR,3PALTU0 avrbit PARCR,2PARDFI avrbit PARCR,1 ; Power Amplifier Ramp Down Frequency InversionPARUFI avrbit PARCR,0 ; Power Amplifier Ramp Up Frequency InversionPHY_RSSI sfr 0x146 ; Receiver Signal Strength Indicator RegisterRX_CRC_VALID avrbit PHY_RSSI,7 ; Received Frame CRC StatusRND_VALUE1 avrbit PHY_RSSI,6 ; Random ValueRND_VALUE0 avrbit PHY_RSSI,5RSSI4 avrbit PHY_RSSI,4 ; Receiver Signal Strength IndicatorRSSI3 avrbit PHY_RSSI,3RSSI2 avrbit PHY_RSSI,2RSSI1 avrbit PHY_RSSI,1RSSI0 avrbit PHY_RSSI,0PHY_ED_LEVEL sfr 0x147 ; Transceiver Energy Detection Level RegisterED_LEVEL7 avrbit PHY_ED_LEVEL,7 ; Energy Detection LevelED_LEVEL6 avrbit PHY_ED_LEVEL,6ED_LEVEL5 avrbit PHY_ED_LEVEL,5ED_LEVEL4 avrbit PHY_ED_LEVEL,4ED_LEVEL3 avrbit PHY_ED_LEVEL,3ED_LEVEL2 avrbit PHY_ED_LEVEL,2ED_LEVEL1 avrbit PHY_ED_LEVEL,1ED_LEVEL0 avrbit PHY_ED_LEVEL,0PHY_CC_CCA sfr 0x148 ; Transceiver Clear Channel Assessment (CCA) Control RegisterCCA_REQUEST avrbit PHY_CC_CCA,7 ; Manual CCA Measurement RequestCCA_MODE1 avrbit PHY_CC_CCA,6 ; Select CCA Measurement ModeCCA_MODE0 avrbit PHY_CC_CCA,5CHANNEL4 avrbit PHY_CC_CCA,4 ; RX/TX Channel SelectionCHANNEL3 avrbit PHY_CC_CCA,3CHANNEL2 avrbit PHY_CC_CCA,2CHANNEL1 avrbit PHY_CC_CCA,1CHANNEL0 avrbit PHY_CC_CCA,0CCA_THRES sfr 0x149 ; Transceiver CCA Threshold Setting RegisterCCA_CS_THRES3 avrbit CCA_THRES,7 ; CS Threshold Level for CCA MeasurementCCA_CS_THRES2 avrbit CCA_THRES,6CCA_CS_THRES1 avrbit CCA_THRES,5CCA_CS_THRES0 avrbit CCA_THRES,4CCA_ED_THRES3 avrbit CCA_THRES,3 ; ED Threshold Level for CCA MeasurementCCA_ED_THRES2 avrbit CCA_THRES,2CCA_ED_THRES1 avrbit CCA_THRES,1CCA_ED_THRES0 avrbit CCA_THRES,0RX_CTRL sfr 0x14a ; Transceiver Receive Control RegisterSDM_MODE1 avrbit RX_CTRL,7 ; Sigma-Delta Modulator Order and Delay CompensationSDM_MODE0 avrbit RX_CTRL,6ACR_MODE avrbit RX_CTRL,5 ; Adjacent Channel Rejection ModeSOFT_MODE avrbit RX_CTRL,4 ; Correlator Soft ModePDT_THRES3 avrbit RX_CTRL,3 ; Receiver Sensitivity ControlPDT_THRES2 avrbit RX_CTRL,2PDT_THRES1 avrbit RX_CTRL,1PDT_THRES0 avrbit RX_CTRL,0SFD_VALUE sfr 0x14b ; Start of Frame Delimiter Value RegisterTRX_CTRL_2 sfr 0x14c ; Transceiver Control Register 2RX_SAFE_MODE avrbit TRX_CTRL_2,7 ; RX Safe ModeOQPSK_DATA_RATE1 avrbit TRX_CTRL_2,1 ; Data Rate SelectionOQPSK_DATA_RATE0 avrbit TRX_CTRL_2,0ANT_DIV sfr 0x14d ; Antenna Diversity Control RegisterANT_SEL avrbit ANT_DIV,7 ; Antenna Diversity Antenna StatusANT_DIV_EN avrbit ANT_DIV,3 ; Enable Antenna DiversityANT_EXT_SW_EN avrbit ANT_DIV,2 ; Enable External Antenna Switch ControlANT_CTRL1 avrbit ANT_DIV,1 ; Static Antenna Diversity Switch ControlANT_CTRL0 avrbit ANT_DIV,0IRQ_MASK sfr 0x14e ; Transceiver Interrupt Enable RegisterAWAKE_EN avrbit IRQ_MASK,7 ; Awake Interrupt EnableTX_END_EN avrbit IRQ_MASK,6 ; TX_END Interrupt EnableAMI_EN avrbit IRQ_MASK,5 ; Address Match Interrupt EnableCCA_ED_DONE_EN avrbit IRQ_MASK,4 ; End of ED Measurement Interrupt EnableRX_END_EN avrbit IRQ_MASK,3 ; RX_END Interrupt EnableRX_START_EN avrbit IRQ_MASK,2 ; RX_START Interrupt EnablePLL_UNLOCK_EN avrbit IRQ_MASK,1 ; PLL Unlock Interrupt EnablePLL_LOCK_EN avrbit IRQ_MASK,0 ; PLL Lock Interrupt EnableIRQ_MASK1 sfr 0xbe ; Transceiver Interrupt Enable Register 1MAF_3_AMI_EN avrbit IRQ_MASK1,4 ; Address Match Interrupt Enable Address Filter 3MAF_2_AMI_EN avrbit IRQ_MASK1,3 ; Address Match Interrupt Enable Address Filter 2MAF_1_AMI_EN avrbit IRQ_MASK1,2 ; Address Match Interrupt Enable Address Filter 1MAF_0_AMI_EN avrbit IRQ_MASK1,1 ; Address Match Interrupt Enable Address Filter 0TX_START_EN avrbit IRQ_MASK1,0 ; Transmit Start Interrupt EnableIRQ_STATUS sfr 0x14f ; Transceiver Interrupt Status RegisterAWAKE avrbit IRQ_STATUS,7 ; Awake Interrupt StatusTX_END avrbit IRQ_STATUS,6 ; TX_END Interrupt StatusAMI avrbit IRQ_STATUS,5 ; Address Match Interrupt StatusCCA_ED_DONE avrbit IRQ_STATUS,4 ; End of ED Measurement Interrupt StatusRX_END avrbit IRQ_STATUS,3 ; RX_END Interrupt StatusRX_START avrbit IRQ_STATUS,2 ; RX_START Interrupt StatusPLL_UNLOCK avrbit IRQ_STATUS,1 ; PLL Unlock Interrupt StatusPLL_LOCK avrbit IRQ_STATUS,0 ; PLL Lock Interrupt StatusIRQ_STATUS1 sfr 0xbf ; Transceiver Interrupt Status Register 1MAF_3_AMI avrbit IRQ_STATUS1,4 ; Address Match Interrupt Status Address Filter 3MAF_2_AMI avrbit IRQ_STATUS1,3 ; Address Match Interrupt Status Address Filter 2MAF_1_AMI avrbit IRQ_STATUS1,2 ; Address Match Interrupt Status Address Filter 1MAF_0_AMI avrbit IRQ_STATUS1,1 ; Address Match Interrupt Status Address Filter 0TX_START avrbit IRQ_STATUS1,0 ; Transmit Start Interrupt StatusVREG_CTRL sfr 0x150 ; Voltage Regulator Control and Status RegisterAVREG_EXT avrbit VREG_CTRL,7 ; Use External AVDD RegulatorAVDD_OK avrbit VREG_CTRL,6 ; AVDD Supply Voltage ValidAVREG_TRIM1 avrbit VREG_CTRL,5 ; Adjust AVDD Supply VoltageAVREG_TRIM0 avrbit VREG_CTRL,4DVREG_EXT avrbit VREG_CTRL,3 ; Use External DVDD RegulatorDVDD_OK avrbit VREG_CTRL,2 ; DVDD Supply Voltage ValidDVREG_TRIM1 avrbit VREG_CTRL,1 ; Adjust DVDD Supply VoltageDVREG_TRIM0 avrbit VREG_CTRL,0BATMON sfr 0x151 ; Battery Monitor Control and Status RegisterBAT_LOW avrbit BATMON,7 ; Battery Monitor Interrupt StatusBAT_LOW_EN avrbit BATMON,6 ; Battery Monitor Interrupt EnableBATMON_OK avrbit BATMON,5 ; Battery Monitor StatusBATMON_HR avrbit BATMON,4 ; Battery Monitor Voltage RangeBATMON_VTH3 avrbit BATMON,3 ; Battery Monitor Threshold VoltageBATMON_VTH2 avrbit BATMON,2BATMON_VTH1 avrbit BATMON,1BATMON_VTH0 avrbit BATMON,0XOSC_CTRL sfr 0x152 ; Crystal Oscillator Control RegisterXTAL_MODE3 avrbit XOSC_CTRL,7 ; Crystal Oscillator Operating ModeXTAL_MODE2 avrbit XOSC_CTRL,6XTAL_MODE1 avrbit XOSC_CTRL,5XTAL_MODE0 avrbit XOSC_CTRL,4XTAL_TRIM3 avrbit XOSC_CTRL,3 ; Crystal Oscillator Load Capacitance TrimmingXTAL_TRIM2 avrbit XOSC_CTRL,2XTAL_TRIM1 avrbit XOSC_CTRL,1XTAL_TRIM0 avrbit XOSC_CTRL,0RX_SYN sfr 0x155 ; Transceiver Receiver Sensitivity Control RegisterRX_PDT_DIS avrbit RX_SYN,7 ; PrEvent Frame ReceptionRX_OVERRIDE avrbit RX_SYN,6 ; Receiver Override FunctionRXO_CFG1 avrbit RX_SYN,5 ; RX_OVERRIDE ConfigurationRXO_CFG0 avrbit RX_SYN,4RX_PDT_LEVEL3 avrbit RX_SYN,3 ; Reduce Receiver SensitivityRX_PDT_LEVEL2 avrbit RX_SYN,2RX_PDT_LEVEL1 avrbit RX_SYN,1RX_PDT_LEVEL0 avrbit RX_SYN,0XAH_CTRL_1 sfr 0x157 ; Transceiver Acknowledgment Frame Control Register 1AACK_FLTR_RES_FT avrbit XAH_CTRL_1,5 ; Filter Reserved FramesAACK_UPLD_RES_FT avrbit XAH_CTRL_1,4 ; Process Reserved FramesAACK_ACK_TIME avrbit XAH_CTRL_1,2 ; Reduce Acknowledgment TimeAACK_PROM_MODE avrbit XAH_CTRL_1,1 ; Enable Promiscuous ModeFTN_CTRL sfr 0x158 ; Transceiver Filter Tuning Control RegisterFTN_START avrbit FTN_CTRL,7 ; Start Calibration Loop of Filter Tuning NetworkFTN_ROUND avrbit FTN_CTRL,6 ; Round Filter Tuning Calibration ResultFTNV5 avrbit FTN_CTRL,5 ; Filter Tuning Calibration ResultFTNV4 avrbit FTN_CTRL,4FTNV3 avrbit FTN_CTRL,3FTNV2 avrbit FTN_CTRL,2FTNV1 avrbit FTN_CTRL,1FTNV0 avrbit FTN_CTRL,0PLL_CF sfr 0x15a ; Transceiver Center Frequency Calibration Control RegisterPLL_CF_START avrbit PLL_CF,7 ; Start Center Frequency CalibrationEN_PLL_CF avrbit PLL_CF,6 ; Enable Center Frequency TuningPLL_VMOD_TUNE1 avrbit PLL_CF,5 ; VCO Modulation TuningPLL_VMOD_TUNE0 avrbit PLL_CF,4PLL_CF3 avrbit PLL_CF,3 ; Center Frequency Control WordPLL_CF2 avrbit PLL_CF,2PLL_CF1 avrbit PLL_CF,1PLL_CF0 avrbit PLL_CF,0PLL_DCU sfr 0x15b ; Transceiver Delay Cell Calibration Control RegisterPLL_DCU_START avrbit PLL_DCU,7 ; Start Delay Cell CalibrationPLL_DCUW5 avrbit PLL_DCU,5 ; Delay Range SettingPLL_DCUW4 avrbit PLL_DCU,4PLL_DCUW3 avrbit PLL_DCU,3PLL_DCUW2 avrbit PLL_DCU,2PLL_DCUW1 avrbit PLL_DCU,1PLL_DCUW0 avrbit PLL_DCU,0CC_CTRL_0 sfr 0x153 ; Channel Control Register 0CC_NUMBER7 avrbit CC_NUMBER7,7 ; Channel NumberCC_NUMBER6 avrbit CC_NUMBER7,6CC_NUMBER5 avrbit CC_NUMBER7,5CC_NUMBER4 avrbit CC_NUMBER7,4CC_NUMBER3 avrbit CC_NUMBER7,3CC_NUMBER2 avrbit CC_NUMBER7,2CC_NUMBER1 avrbit CC_NUMBER7,1CC_NUMBER0 avrbit CC_NUMBER7,0CC_CTRL_1 sfr 0x154 ; Channel Control Register 1CC_BAND3 avrbit CC_CTRL_1,3 ; Channel BandCC_BAND2 avrbit CC_CTRL_1,2CC_BAND1 avrbit CC_CTRL_1,1CC_BAND0 avrbit CC_CTRL_1,0TRX_RPC sfr 0x156 ; Transceiver Reduced Power Consumption ControlRX_RPC_CTRL1 avrbit TRX_RPC,7 ; Smart Receiving Mode TimingRX_RPC_CTRL0 avrbit TRX_RPC,6RX_RPC_EN avrbit TRX_RPC,5 ; Receiver Smart Receiving Mode EnablePDT_RPC_EN avrbit TRX_RPC,4 ; Smart Receiving Mode Reduced Sensitivity EnablePLL_RPC_EN avrbit TRX_RPC,3 ; PLL Smart Receiving Mode EnableIPAN_RPC_EN avrbit TRX_RPC,1 ; Smart Receiving Mode IPAN Handling EnableXAH_RPC_EN avrbit TRX_RPC,0 ; Smart Receiving in Extended Operating Modes EnablePART_NUM sfr 0x15c ; Device Identification Register (Part Number)VERSION_NUM sfr 0x15d ; Device Identification Register (Version Number)MAN_ID_0 sfr 0x15e ; Device Identification Register (Manufacture ID Low Byte)MAN_ID_1 sfr 0x15f ; Device Identification Register (Manufacture ID High Byte)SHORT_ADDR_0 sfr 0x160 ; Transceiver MAC Short Address Register (Low Byte)SHORT_ADDR_1 sfr 0x161 ; Transceiver MAC Short Address Register (High Byte)PAN_ID_0 sfr 0x162 ; Transceiver Personal Area Network ID Register (Low Byte)PAN_ID_1 sfr 0x163 ; Transceiver Personal Area Network ID Register (High Byte)IEEE_ADDR_0 sfr 0x164 ; Transceiver MAC IEEE Address RegisterIEEE_ADDR_1 sfr 0x165IEEE_ADDR_2 sfr 0x166IEEE_ADDR_3 sfr 0x167IEEE_ADDR_4 sfr 0x168IEEE_ADDR_5 sfr 0x169IEEE_ADDR_6 sfr 0x16aIEEE_ADDR_7 sfr 0x16bXAH_CTRL_0 sfr 0x16c ; Transceiver Extended Operating Mode Control RegisterMAX_FRAME_RETRIES3 avrbit XAH_CTRL_0,7 ; Maximum Number of Frame Retransmission AttemptsMAX_FRAME_RETRIES2 avrbit XAH_CTRL_0,6MAX_FRAME_RETRIES1 avrbit XAH_CTRL_0,5MAX_FRAME_RETRIES0 avrbit XAH_CTRL_0,4MAX_CSMA_RETRIES2 avrbit XAH_CTRL_0,3 ; Maximum Number of CSMA-CA Procedure Repetition AttemptsMAX_CSMA_RETRIES1 avrbit XAH_CTRL_0,2MAX_CSMA_RETRIES0 avrbit XAH_CTRL_0,1SLOTTED_OPERATION avrbit XAH_CTRL_0,0 ; Set Slotted AcknowledgmentCSMA_SEED_0 sfr 0x16d ; Transceiver CSMA-CA Random Number Generator Seed RegisterCSMA_SEED_1 sfr 0x16e ; Transceiver Acknowledgment Frame Control Register 2AACK_FVN_MODE1 avrbit CSMA_SEED_1,7 ; Acknowledgment Frame Filter ModeAACK_FVN_MODE0 avrbit CSMA_SEED_1,6AACK_SET_PD avrbit CSMA_SEED_1,5 ; Set Frame Pending Sub-fieldAACK_DIS_ACK avrbit CSMA_SEED_1,4 ; Disable Acknowledgment Frame TransmissionAACK_I_AM_COORD avrbit CSMA_SEED_1,3 ; Set Personal Area Network CoordinatorCSMA_SEED_12 avrbit CSMA_SEED_1,2 ; Seed Value for CSMA Random Number GeneratorCSMA_SEED_11 avrbit CSMA_SEED_1,1CSMA_SEED_10 avrbit CSMA_SEED_1,0CSMA_BE sfr 0x16f ; Transceiver CSMA-CA Back-off Exponent Control RegisterMAX_BE3 avrbit CSMA_BE,7 ; Maximum Back-off ExponentMAX_BE2 avrbit CSMA_BE,6MAX_BE1 avrbit CSMA_BE,5MAX_BE0 avrbit CSMA_BE,4MIN_BE3 avrbit CSMA_BE,3 ; Minimum Back-off ExponentMIN_BE2 avrbit CSMA_BE,2MIN_BE1 avrbit CSMA_BE,1MIN_BE0 avrbit CSMA_BE,0MAFCR0 sfr 0x10c ; Multiple Address Filter Configuration Register 0MAF3EN avrbit MAFCR0,3 ; Multiple Address Filter 3 EnableMAF2EN avrbit MAFCR0,2 ; Multiple Address Filter 2 EnableMAF1EN avrbit MAFCR0,1 ; Multiple Address Filter 1 EnableMAF0EN avrbit MAFCR0,0 ; Multiple Address Filter 0 EnableMAFCR1 sfr 0x10d ; Multiple Address Filter Configuration Register 1AACK_3_SET_PD avrbit MAFCR1,7 ; Set Data Pending bit for address Filter 3AACK_3_I_AM_COORD avrbit MAFCR1,6 ; Enable PAN Coordinator Mode for address Filter 3AACK_2_SET_PD avrbit MAFCR1,5 ; Set Data Pending bit for address Filter 2AACK_2_I_AM_COORD avrbit MAFCR1,4 ; Enable PAN Coordinator Mode for address Filter 2AACK_1_SET_PD avrbit MAFCR1,3 ; Set Data Pending bit for address Filter 1AACK_1_I_AM_COORD avrbit MAFCR1,2 ; Enable PAN Coordinator Mode for address Filter 1AACK_0_SET_PD avrbit MAFCR1,1 ; Set Data Pending bit for address Filter 0AACK_0_I_AM_COORD avrbit MAFCR1,0 ; Enable PAN Coordinator Mode for address Filter 0MAFPA0H sfr 0x111 ; Transceiver Personal Area Network ID Register for Frame Filter 0 (High Byte)MAFPA0L sfr 0x110 ; Transceiver Personal Area Network ID Register for Frame Filter 0 (Low Byte)MAFPA1H sfr 0x115 ; Transceiver Personal Area Network ID Register for Frame Filter 1 (High Byte)MAFPA1L sfr 0x114 ; Transceiver Personal Area Network ID Register for Frame Filter 1 (Low Byte)MAFPA2H sfr 0x119 ; Transceiver Personal Area Network ID Register for Frame Filter 2 (High Byte)MAFPA2L sfr 0x118 ; Transceiver Personal Area Network ID Register for Frame Filter 2 (Low Byte)MAFPA3H sfr 0x11d ; Transceiver Personal Area Network ID Register for Frame Filter 3 (High Byte)MAFPA3L sfr 0x11c ; Transceiver Personal Area Network ID Register for Frame Filter 3 (Low Byte)MAFSA0H sfr 0x10f ; Transceiver MAC Short Address Register for Frame Filter 0 (High Byte)MAFSA0L sfr 0x10e ; Transceiver MAC Short Address Register for Frame Filter 0 (Low Byte)MAFSA1H sfr 0x113 ; Transceiver MAC Short Address Register for Frame Filter 1 (High Byte)MAFSA1L sfr 0x112 ; Transceiver MAC Short Address Register for Frame Filter 1 (Low Byte)MAFSA2H sfr 0x117 ; Transceiver MAC Short Address Register for Frame Filter 2 (High Byte)MAFSA2L sfr 0x116 ; Transceiver MAC Short Address Register for Frame Filter 2 (Low Byte)MAFSA3H sfr 0x11b ; Transceiver MAC Short Address Register for Frame Filter 3 (High Byte)MAFSA3L sfr 0x11a ; Transceiver MAC Short Address Register for Frame Filter 3 (Low Byte)TST_CTRL_DIGI sfr 0x176 ; Transceiver Digital Test Control RegisterTST_CTRL_DIG_7 avrbit TST_CTRL_DIGI,7 ; Disable Receiver Baseband Frequency SynthesisTST_CTRL_DIG_6 avrbit TST_CTRL_DIGI,6 ; Disable Receiver Baseband Drift CompensationTST_CTRL_DIG_5 avrbit TST_CTRL_DIGI,5 ; Enable Switch of Transceiver FIFOTST_CTRL_DIG_4 avrbit TST_CTRL_DIGI,4 ; Switch Receiver Input DataTST_CTRL_DIG3 avrbit TST_CTRL_DIGI,3 ; Digital Test Controller RegisterTST_CTRL_DIG2 avrbit TST_CTRL_DIGI,2TST_CTRL_DIG1 avrbit TST_CTRL_DIGI,1TST_CTRL_DIG0 avrbit TST_CTRL_DIGI,0TST_RX_LENGTH sfr 0x17b ; Transceiver Received Frame Length RegisterTRXFBST sfr 0x180 ; Start of Frame BufferTRXFBEND sfr 0x1ff ; End of Frame BufferTRXPR sfr 0x139 ; Transceiver Pin RegisterATBE avrbit TRXPR,3 ; Analog Test-Bus EnableTRXTST avrbit TRXPR,2 ; Transceiver Test-Mode EnableSLPTR avrbit TRXPR,1 ; Multi-Purpose Transceiver Control BitTRXRST avrbit TRXPR,0 ; Force Transceiver Resetrestore ; re-enable listingendif ; __tr24inc