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ifndef __54xxsecinc ; avoid multiple inclusion__54xxsecinc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File 54XXSEC.INC *;* *;* Contains SFR and Bit Definitions for ColdFire MCF54xx Security Engine *;* *;****************************************************************************; Arbiter/Controller Control register spaceMBAR_SCTRL equ MBAR_SEC+$1000EUACRH equ MBAR_SCTRL+$00 ; EU Assignment Control Register High (32b)RNG cffield EUACRH,24,4 ; RNG AssignmentMDEU cffield EUACRH,8,4 ; MDEU AssignmentAFEU cffield EUACRH,0,4 ; AFEU AssignmentEUACRL equ MBAR_SCTRL+$04 ; EU Assignment Control Register Low (32b)DEU cffield EUACRL,24,4 ; DEU AssignmentAESU cffield EUACRL,16,4 ; AESU AssignmentSIMRH equ MBAR_SCTRL+$08 ; SEC Interrupt Mask Register High (32b)CHA_1_ERR cfbit SIMRH,31 ; Channel 1 Error Interrupt MaskCHA_1_DN cfbit SIMRH,30 ; Channel 1 Done Interrupt MaskCHA_0_ERR cfbit SIMRH,29 ; Channel 0 Error Interrupt MaskCHA_0_DN cfbit SIMRH,28 ; Channel 0 Done Interrupt MaskAERR cfbit SIMRH,27 ; Assignment Error Interrupt MaskSIMRL equ MBAR_SCTRL+$0C ; SEC Interrupt Mask Register Low (32b)RNG_ERR cfbit SIMRL,25 ; RNG Error Interrupt MaskRNG_DN cfbit SIMRL,24 ; RNG Done Interrupt MaskAFEU_ERR cfbit SIMRL,21 ; AFEU Error Interrupt MaskAFEU_DN cfbit SIMRL,20 ; AFEU Done Interrupt MaskMDEU_ERR cfbit SIMRL,17 ; MDEU Error Interrupt MaskMDEU_DN cfbit SIMRL,16 ; MDEU Done Interrupt MaskAESU_ERR cfbit SIMRL,13 ; AESU Error Interrupt MaskAESU_DN cfbit SIMRL,12 ; AESU Done Interrupt MaskDEU_ERR cfbit SIMRL,9 ; DEU Error Interrupt MaskDEU_DN cfbit SIMRL,8 ; DEU Done Interrupt MaskTEA cfbit SIMRL,6 ; Transfer Error Acknowledge MaskSISRH equ MBAR_SCTRL+$10 ; SEC Interrupt Status Register High (32b)CHA_1_ERR cfbit SISRH,31 ; Channel 1 Error Interrupt StatusCHA_1_DN cfbit SISRH,30 ; Channel 1 Done Interrupt StatusCHA_0_ERR cfbit SISRH,29 ; Channel 0 Error Interrupt StatusCHA_0_DN cfbit SISRH,28 ; Channel 0 Done Interrupt StatusAERR cfbit SISRH,27 ; Assignment Error Interrupt StatusSISRL equ MBAR_SCTRL+$14 ; SEC Interrupt Status Register Low (32b)RNG_ERR cfbit SISRL,25 ; RNG Error Interrupt StatusRNG_DN cfbit SISRL,24 ; RNG Done Interrupt StatusAFEU_ERR cfbit SISRL,21 ; AFEU Error Interrupt StatusAFEU_DN cfbit SISRL,20 ; AFEU Done Interrupt StatusMDEU_ERR cfbit SISRL,17 ; MDEU Error Interrupt StatusMDEU_DN cfbit SISRL,16 ; MDEU Done Interrupt StatusAESU_ERR cfbit SISRL,13 ; AESU Error Interrupt StatusAESU_DN cfbit SISRL,12 ; AESU Done Interrupt StatusDEU_ERR cfbit SISRL,9 ; DEU Error Interrupt StatusDEU_DN cfbit SISRL,8 ; DEU Done Interrupt StatusTEA cfbit SISRL,6 ; Transfer Error Acknowledge StatusSICRH equ MBAR_SCTRL+$18 ; SEC Interrupt Control Register High (32b)CHA_1_ERR cfbit SICRH,31 ; Channel 1 Error Interrupt ControlCHA_1_DN cfbit SICRH,30 ; Channel 1 Done Interrupt ControlCHA_0_ERR cfbit SICRH,29 ; Channel 0 Error Interrupt ControlCHA_0_DN cfbit SICRH,28 ; Channel 0 Done Interrupt ControlAERR cfbit SICRH,27 ; Assignment Error Interrupt ControlSICRL equ MBAR_SCTRL+$1C ; SEC Interrupt Control Register Low (32b)RNG_ERR cfbit SICRL,25 ; RNG Error Interrupt ControlRNG_DN cfbit SICRL,24 ; RNG Done Interrupt ControlAFEU_ERR cfbit SICRL,21 ; AFEU Error Interrupt ControlAFEU_DN cfbit SICRL,20 ; AFEU Done Interrupt ControlMDEU_ERR cfbit SICRL,17 ; MDEU Error Interrupt ControlMDEU_DN cfbit SICRL,16 ; MDEU Done Interrupt ControlAESU_ERR cfbit SICRL,13 ; AESU Error Interrupt ControlAESU_DN cfbit SICRL,12 ; AESU Done Interrupt ControlDEU_ERR cfbit SICRL,9 ; DEU Error Interrupt ControlDEU_DN cfbit SICRL,8 ; DEU Done Interrupt ControlTEA cfbit SICRL,6 ; Transfer Error Acknowledge ControlSIDR equ MBAR_SCTRL+$20 ; SEC ID Register (32b)VERSION cffield SIDR,0,32 ; Version of the SECEUASRH equ MBAR_SCTRL+$28 ; EU Assignment Status Register High (32b)RNG cffield EUASRH,24,4 ; Actual RNG AssignmentMDEU cffield EUASRH,8,4 ; Actual MDEU AssignmentAFEU cffield EUASRH,0,4 ; Actual AFEU AssignmentEUASRL equ MBAR_SCTRL+$2C ; EU Assignment Status Register Low (32b)DESU cffield EUASRL,24,4 ; Actual DEU AssignmentAESU cffield EUASRL,16,4 ; Actual AESU AssignmentSMCR equ MBAR_SCTRL+$30 ; SEC Master Control Register (32b)SWR cfbit SMCR,24 ; Software ResetCURR_CHAN cffield SMCR,4,4 ; Current Channel.MEAR equ MBAR_SCTRL+$38 ; Master Error Address Register (32b)ADDRESS cffield MEAR,0,32 ; Target address of the transaction when TEA was received.; Crypto-channels__defsecchan macro N,BaseCCCR{N} equ Base+$0c ; Crypto-Channel Configuration Register n (32b)BURST_SIZE cffield CCCR{N},8,3 ; Burst SizeWE cfbit CCCR{N},4 ; Writeback Enable.NE cfbit CCCR{N},3 ; Fetch Next Descriptor Enable.NT cfbit CCCR{N},2 ; Channel DONE Notification Type.CDIE cfbit CCCR{N},1 ; Channel DONE Interrupt Enable.RST cfbit CCCR{N},0 ; Reset Crypto-Channel.CCPSRH{N} equ Base+$10 ; Crypto-Channel Pointer Status Register High n (32b)STATE cffield CCPSRH{N},0,8 ; State of the crypto-channel state machine.CCPSRL{N} equ Base+$14 ; Crypto-Channel Pointer Status Register Low n (32b)STAT cfbit CCPSRL{N},26 ; Crypto-Channel Static Mode Enable.MI cfbit CCPSRL{N},25 ; Multi_EU_IN.MO cfbit CCPSRL{N},24 ; Multi_EU_OUT.PR cfbit CCPSRL{N},23 ; Primary request.SR cfbit CCPSRL{N},22 ; Secondary request.PG cfbit CCPSRL{N},21 ; Primary EU granted.SG cfbit CCPSRL{N},20 ; Secondary EU granted.PRD cfbit CCPSRL{N},19 ; Primary EU reset done.SRD cfbit CCPSRL{N},18 ; Secondary EU reset done.PD cfbit CCPSRL{N},17 ; Primary EU done.SD cfbit CCPSRL{N},16 ; Secondary EU done.TEA cfbit CCPSRL{N},13 ; Transfer error acknowledge.PERR cfbit CCPSRL{N},12 ; Pointer not complete error.DERR cfbit CCPSRL{N},10 ; Descriptor error. TheSERR cfbit CCPSRL{N},9 ; Static assignment error.EUERR cfbit CCPSRL{N},8 ; EU error.PAIR_PTR cffield CCPSRL{N},0,8 ; Descriptor buffer register length/pointer pairCDPR{N} equ Base+$44 ; Crypto-Channel Current Descriptor Pointer Register n (32b)FR{N} equ Base+$4c ; Fetch Register n (32b)FETCH_ADDR cffield FR{N},0,32 ; Fetch address.CDBUF{N} equ Base+$80 ; Crypto-Channel Descriptor Buffer n (8*32b)endmMBAR_SCHAN0 equ MBAR_SEC+$2000__defsecchan "0",MBAR_SCHAN0; Crypto-channel 2MBAR_SCHAN1 equ MBAR_SEC+$3000__defsecchan "1",MBAR_SCHAN1; ArcFour Execution UnitMBAR_AFEU equ MBAR_SEC+$8000AFRCR equ MBAR_AFEU+$18 ; AFEU Reset Control Register (32b)AFSR equ MBAR_AFEU+$28 ; AFEU Status Register (32b)AFISR equ MBAR_AFEU+$30 ; AFEU Interrupt Status Register (32b)AFIMR equ MBAR_AFEU+$38 ; AFEU Interrupt Mask Register (32b)irp Reg,AFISR,AFIMRME cfbit Reg,31 ; Mode error.AE cfbit Reg,30 ; Address error.OFE cfbit Reg,29 ; Output FIFO error.IFE cfbit Reg,28 ; Input FIFO error.IFO cfbit Reg,26 ; Input FIFO overflow.OFU cfbit Reg,25 ; Output FIFO underflow.IE cfbit Reg,20 ; Internal error.ERE cfbit Reg,19 ; Early read error.CE cfbit Reg,18 ; Context error.KSE cfbit Reg,17 ; Key size error.DSE cfbit Reg,16 ; Data size error.endm; DES Execution UnitMBAR_DEU equ MBAR_SEC+$a000DRCR equ MBAR_DEU+$18 ; DEU Reset Control Register (32b)DEU_DSR equ MBAR_DEU+$28 ; DEU Status Register (32b)DISR equ MBAR_DEU+$30 ; DEU Interrupt Status Register (32b)DEU_DIMR equ MBAR_DEU+$38 ; DEU Interrupt Mask Register (32b)irp Reg,DISR,DIMRME cfbit Reg,31 ; Mode error.AE cfbit Reg,30 ; Address error.OFE cfbit Reg,29 ; Output FIFO error.IFE cfbit Reg,28 ; Input FIFO error.IFO cfbit Reg,26 ; Input FIFO overflow.OFU cfbit Reg,25 ; Output FIFO underflow.KPE cfbit Reg,21 ; Key Parity Error.IE cfbit Reg,20 ; Internal error.ERE cfbit Reg,19 ; Early read error.CE cfbit Reg,18 ; Context error.KSE cfbit Reg,17 ; Key size error.DSE cfbit Reg,16 ; Data size error.endm; Message Digest Execution UnitMBAR_MDEU equ MBAR_SEC+$c000MDRCR equ MBAR_MDEU+$18 ; MDEU Reset Control Register (32b)MDSR equ MBAR_MDEU+$28 ; MDEU Status Register (32b)MDISR equ MBAR_MDEU+$30 ; MDEU Interrupt Status Register (32b)MDIMR equ MBAR_MDEU+$38 ; MDEU Interrupt Mask Register (32b)irp Reg,MDISR,MDIMRME cfbit Reg,31 ; Mode Error.AE cfbit Reg,30 ; Address Error.IFO cfbit Reg,26 ; Input FIFO Overflow.IE cfbit Reg,20 ; Internal Error.ERE cfbit Reg,19 ; Early Read Error.CE cfbit Reg,18 ; Context Error.KSE cfbit Reg,17 ; Key Size Error.DSE cfbit Reg,16 ; Data Size Error.endm; Random Number GeneratorMBAR_RNG equ MBAR_SEC+$e000RNGRCR equ MBAR_RNG+$18 ; RNG Reset Control Register (32b)RNGSR equ MBAR_RNG+$28 ; RNG Status Register (32b)RNGISR equ MBAR_RNG+$30 ; RNG Interrupt Status Register (32b)RNGIMR equ MBAR_RNG+$38 ; RNG Interrupt Mask Register (32b)irp Reg,RNGISR,RNGIMRME cfbit Reg,31 ; Mode Error.AE cfbit Reg,30 ; Address Error.OFU cfbit Reg,25 ; Output FIFO underflow.IE cfbit Reg,20 ; Internal error.endm; AES Execution UnitMBAR_AESU equ MBAR_SEC+$12000AESRCR equ MBAR_AESU+$18 ; AESU Reset Control Register (32b)AESSR equ MBAR_AESU+$28 ; AESU Status Register (32b)AESISR equ MBAR_AESU+$30 ; AESU Interrupt Status Register (32b)AESIMR equ MBAR_AESU+$38 ; AESU Interrupt Mask Register (32b)irp Reg,AESISR,AESIMRME cfbit Reg,31 ; Mode Error.AE cfbit Reg,30 ; Address Error.OFE cfbit Reg,29 ; Output FIFO error.IFE cfbit Reg,28 ; Input FIFO error.IFO cfbit Reg,26 ; Input FIFO Overflow.OFU cfbit Reg,25 ; Output FIFO underflow.IE cfbit Reg,20 ; Internal Error.ERE cfbit Reg,19 ; Early Read Error.CE cfbit Reg,18 ; Context Error.KSE cfbit Reg,17 ; Key Size Error.DSE cfbit Reg,16 ; Data Size Error.endm; Common Bits in all EUsirp Reg,AFRCR,DRCR,MDRCR,RNGRCR,AESRCRRI cfbit Reg,26 ; Reset interrupt.MI cfbit Reg,25 ; Module initialization.SR cfbit Reg,24 ; Software reset.endmirp Reg,AFSR,DSR,MDSR,RNGSR,AESSRHALT cfbit Reg,29 ; Halt.IFW cfbit Reg,28 ; Input FIFO writable. (not on RNG)OFR cfbit Reg,27 ; Output FIFO readable. (not on MDEEU)IE cfbit Reg,26 ; Interrupt error.ID cfbit Reg,25 ; Interrupt done. (not on RNG)RD cfbit Reg,24 ; Reset done.endmrestore ; re-enable listingendif ; __54xxsecinc