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ifndef __mcf51qminc ; avoid multiple inclusion__mcf51qminc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File MCF51QM.INC *;* *;* Contains SFR and Bit Definitions for ColdFire MCF51QM *;* *;****************************************************************************MBAR equ $ffff8000;----------------------------------------------------------------------------; Rapid General Purpose I/OMBAR_RGPIO equ $00c00000RGPIO_DIR equ MBAR_RGPIO+$00 ; RGPIO Data Direction Register (16b)DIR cffield RGPIO_DIR,0,15 ; Data directionRGPIO_DATA equ MBAR_RGPIO+$02 ; RGPIO Data Register (16b)DATA cffield RGPIO_DATA,0,15 ; RGPIO dataRGPIO_ENB equ MBAR_RGPIO+$04 ; RGPIO Pin Enable Register (16b)ENB cffield RGPIO_ENB,0,15 ; Enable pin for RGPIORGPIO_CLR equ MBAR_RGPIO+$06 ; RGPIO Clear Data Register (16b)CLR cffield RGPIO_CLR,0,15 ; Clear dataRGPIO_DIR_RO equ MBAR_RGPIO+$08 ; RGPIO Data Direction Register (ro) (16b)DIR_RO cffield RGPIO_DIR_RO,0,15 ; Data directionRGPIO_SET equ MBAR_RGPIO+$0A ; RGPIO Set Data Register (8b)SET cffield RGPIO_SET,0,15 ; Set dataRGPIO_DIR_RO_2 equ MBAR_RGPIO+$0C ; RGPIO Data Direction Register (ro, once again?) (8b)DIR_RO_2 cffield RGPIO_DIR_RO_2,0,15 ; Data directionRGPIO_TOG equ MBAR_RGPIO+$0E ; RGPIO Toggle Data Register (8b)TOG cffield RGPIO_TOG,0,15 ; Toggle data;----------------------------------------------------------------------------; Enhanced General Purpose I/O__defegpio macro ID,BasePT{ID}_D equ Base+$00 ; Port Data Register (8b)__enumbits PT{ID}_D,PTD,8 ; Port data bitsPT{ID}_DD equ Base+$01 ; Port Data Direction Register (8b)__enumbits PT{ID}_DD,PTDD,8 ; Port data direction bitsPT{ID}_PV equ Base+$02 ; Port Pin Value Register (8b)__enumbits PT{ID}_PV,PTPV,8 ; Port pin value bitsendm__defegpio "A",MBAR+$0000__defegpio "B",MBAR+$0010__defegpio "C",MBAR+$0020__defegpio "D",MBAR+$0030__defegpio "E",MBAR+$0040__defegpio "F",MBAR+$0050;----------------------------------------------------------------------------; Register FileMBAR_RF equ MBAR+$0060;----------------------------------------------------------------------------; Port Mux ControlsMBAR_MXC equ MBAR+$0080__defmux macro ID,BasePT{ID}PF1 equ Base+0 ; Port x Pin Function 1 Register (8b){ID}7 cffield PT{ID}PF1,4,4 ; Port x.7 Pin Mux Controls{ID}6 cffield PT{ID}PF1,0,4 ; Port x.6 Pin Mux ControlsPT{ID}PF2 equ Base+1 ; Port x Pin Function 2 Register (8b){ID}5 cffield PT{ID}PF2,4,4 ; Port x.5 Pin Mux Controls{ID}4 cffield PT{ID}PF2,0,4 ; Port x.4 Pin Mux ControlsPT{ID}PF3 equ Base+2 ; Port x Pin Function 3 Register (8b){ID}3 cffield PT{ID}PF3,4,4 ; Port x.3 Pin Mux Controls{ID}2 cffield PT{ID}PF3,0,4 ; Port x.2 Pin Mux ControlsPT{ID}PF4 equ Base+3 ; Port x Pin Function 4 Register (8b){ID}1 cffield PT{ID}PF4,4,4 ; Port x.1 Pin Mux Controls{ID}0 cffield PT{ID}PF4,0,4 ; Port x.0 Pin Mux Controlsendm__defmux "A",MBAR_MXC+$00__defmux "B",MBAR_MXC+$04__defmux "C",MBAR_MXC+$08__defmux "D",MBAR_MXC+$0c__defmux "E",MBAR_MXC+$10__defmux "F",MBAR_MXC+$14;----------------------------------------------------------------------------; External Interrupt ModuleMBAR_IRQ equ MBAR+$00a0IRQ_SC equ MBAR_IRQ+$00 ; Interrupt status and control registerIRQPDD cfbit IRQ_SC,6 ; IRQ pull device disableIRQEDG cfbit IRQ_SC,5 ; IRQ edge selectIRQPE cfbit IRQ_SC,4 ; IRQ pin enableIRQF cfbit IRQ_SC,3 ; IRQ flagIRQACK cfbit IRQ_SC,2 ; IRQ acknowledgeIRQIE cfbit IRQ_SC,1 ; IRQ interrupt enableIRQMOD cfbit IRQ_SC,0 ; IRQ detection mode;----------------------------------------------------------------------------; Low Leakage Wakeup UnitMBAR_LLWU equ MBAR+$00b0LLWU_PE1 equ MBAR_LLWU+$00 ; LLWU Pin Enable 1 register (8b)WUPE3 cffield LLWU_PE1,6,2 ; Wakeup Pin Enable For LLWU_P3WUPE2 cffield LLWU_PE1,4,2 ; Wakeup Pin Enable For LLWU_P2WUPE1 cffield LLWU_PE1,2,2 ; Wakeup Pin Enable For LLWU_P1WUPE0 cffield LLWU_PE1,0,2 ; Wakeup Pin Enable For LLWU_P0LLWU_PE2 equ MBAR_LLWU+$01 ; LLWU Pin Enable 2 register (8b)WUPE7 cffield LLWU_PE2,6,2 ; Wakeup Pin Enable For LLWU_P7WUPE6 cffield LLWU_PE2,4,2 ; Wakeup Pin Enable For LLWU_P6WUPE5 cffield LLWU_PE2,2,2 ; Wakeup Pin Enable For LLWU_P5WUPE4 cffield LLWU_PE2,0,2 ; Wakeup Pin Enable For LLWU_P4LLWU_PE3 equ MBAR_LLWU+$02 ; LLWU Pin Enable 3 register (8b)WUPE11 cffield LLWU_PE3,6,2 ; Wakeup Pin Enable For LLWU_P11WUPE10 cffield LLWU_PE3,4,2 ; Wakeup Pin Enable For LLWU_P10WUPE9 cffield LLWU_PE3,2,2 ; Wakeup Pin Enable For LLWU_P9WUPE8 cffield LLWU_PE3,0,2 ; Wakeup Pin Enable For LLWU_P8LLWU_PE4 equ MBAR_LLWU+$03 ; LLWU Pin Enable 4 register (8b)WUPE15 cffield LLWU_PE4,6,2 ; Wakeup Pin Enable For LLWU_P15WUPE14 cffield LLWU_PE4,4,2 ; Wakeup Pin Enable For LLWU_P14WUPE13 cffield LLWU_PE4,2,2 ; Wakeup Pin Enable For LLWU_P13WUPE12 cffield LLWU_PE4,0,2 ; Wakeup Pin Enable For LLWU_P12LLWU_ME equ MBAR_LLWU+$04 ; LLWU Module Enable register (8b)__enumbits LLWU_ME,WUPE,8 ; Wakeup Module Enable For Module 0..7LLWU_F1 equ MBAR_LLWU+$05 ; LLWU Flag 1 register (8b)__enumbits LLWU_F1,WUF,8 ; Wakeup Flag For LLWU_PnLLWU_F2 equ MBAR_LLWU+$06 ; LLWU Flag 2 register (8b)__enumbits LLWU_F2,WUF,8,8LLWU_F3 equ MBAR_LLWU+$07 ; LLWU Flag 3 register (8b)__enumbits LLWU_F3,MWUF,8 ; Wakeup flag For module nLLWU_FILT1 equ MBAR_LLWU+$08 ; LLWU Pin Filter 1 register (8b)FILTF cfbit LLWU_FILT1,7 ; Filter Detect FlagFILTE cffield LLWU_FILT1,5,2 ; Digital Filter On External PinFILTSEL cffield LLWU_FILT1,0,4 ; Filter Pin SelectLLWU_FILT2 equ MBAR_LLWU+$09 ; LLWU Pin Filter 2 register (8b)FILTF cfbit LLWU_FILT2,7 ; Filter Detect FlagFILTE cffield LLWU_FILT2,5,2 ; Digital Filter On External PinFILTSEL cffield LLWU_FILT2,0,4 ; Filter Pin SelectLLWU_RST equ MBAR_LLWU+$0A ; LLWU Reset Enable register (8b)LLRSTE cfbit LLWU_RST,1 ; Low-Leakage Mode RESET EnableRSTFILT cfbit LLWU_RST,0 ; Digital Filter On RESET Pin;----------------------------------------------------------------------------; System Integration ModuleMBAR_SIM equ MBAR+$00c0SIM_SOPT1 equ MBAR_SIM+$00 ; System Options Register 1 (8b)REGE cfbit SIM_SOPT1,7 ; Voltage Regulator enableSSTB cfbit SIM_SOPT1,6 ; Voltage Regulator standby in stop modesVSTB cfbit SIM_SOPT1,5 ; Voltage Regulator standby in run/wait modesSIM_SOPT2 equ MBAR_SIM+$01 ; System Options Register 2 (8b)RAMSIZE cffield SIM_SOPT2,4,4 ; Size of RAM arraySIM_SOPT3 equ MBAR_SIM+$02 ; System Options Register 3 (8b)SWE cfbit SIM_SOPT3,1 ; Standby write enableRWE cfbit SIM_SOPT3,0 ; Voltage Regulator write enableSIM_SOPT4 equ MBAR_SIM+$03 ; System Options Register 4 (8b)STOPE cfbit SIM_SOPT4,5 ; Stop mode enableWAITE cfbit SIM_SOPT4,4 ; Wait mode enableVLLDBGRE cfbit SIM_SOPT4,0 ; Very Low Leakage Debug Request upon WakeupSIM_SOPT5 equ MBAR_SIM+$04 ; System Options Register 5 (8b)MECS cffield SIM_SOPT5,2,2 ; MTIM16 external clock source selectF1ECS cfbit SIM_SOPT5,1 ; FTM1 external clock selectF0ECS cfbit SIM_SOPT5,0 ; FTM0 external clock selectSIM_SOPT6 equ MBAR_SIM+$05 ; System Options Register 6 (8b)MBSL cffield SIM_SOPT6,6,2 ; Mini-FlexBus security levelMTBASE1 cffield SIM_SOPT6,4,2 ; UART1 TX modulation time base selectRX1IN cfbit SIM_SOPT6,3 ; UART1 RX input pin selectionMODTX1 cfbit SIM_SOPT6,2 ; Modulate TPTF6PAD cfbit SIM_SOPT6,1 ; PTF6 double pad strengthPTC5PAD cfbit SIM_SOPT6,0 ; PTC5 pad double pad strengthSIM_SOPT7 equ MBAR_SIM+$06 ; System Options Register 7 (8b)ADTRGS cfbit SIM_SOPT7,6 ; ADC hardware trigger sourceACFTM cfbit SIM_SOPT7,5 ; CMP output connection to FTM0 Ch0I2CDR2 cfbit SIM_SOPT7,4 ; I2C Link for I2C2 and I2C3I2CDR0 cfbit SIM_SOPT7,3 ; I2C Link for I2C0 and I2C1FTM1SYNC cfbit SIM_SOPT7,1 ; FTM1 synchronization triggerFTM0SYNC cfbit SIM_SOPT7,0 ; FTM0 synchronization triggerSIM_COPC equ MBAR_SIM+$0A ; COP Control Register (8b)COPT cffield SIM_COPC,2,2 ; COP watchdog timeoutCOPCLKS cfbit SIM_COPC,1 ; COP watchdog clock selectCOPW cfbit SIM_COPC,0 ; COP windowed modeSIM_SRVCOP equ MBAR_SIM+$0B ; Service COP Register (8b)SRVCOP cffield SIM_SRVCOP,0,7SIM_OSC1 equ MBAR_SIM+$0D ; Oscillator 1 Control Register (8b)OSC1EN cfbit SIM_OSC1,7 ; Oscillator 1 enableOSC1RANGE cffield SIM_OSC1,3,2 ; Frequency range selectOSC1HGO cfbit SIM_OSC1,2 ; High gain oscillator selectOSC1EREFS cfbit SIM_OSC1,1 ; External reference selectSIM_SDID equ MBAR_SIM+$10 ; Device Identification High Register (16b)SIM_SDIDH equ MBAR_SIM+$10 ; Device Identification High Register (8b)SIM_SDIDL equ MBAR_SIM+$11 ; Device Identification Low Register (8b)REV cffield SIM_SDIDH,4,4 ; Device Revision NumberID cffield SIM_SDID,0,11 ; Device identification numberSIM_SCGC1 equ MBAR_SIM+$12 ; Clock Gate Control Register 1 (8b)I2C3 cfbit SIM_SCGC1,7 ; I2C3 clock gate controlI2C2 cfbit SIM_SCGC1,6 ; I2C2 clock gate controlI2C1 cfbit SIM_SCGC1,5 ; I2C1 clock gate controlI2C0 cfbit SIM_SCGC1,4 ; I2C0 clock gate controlSPI1 cfbit SIM_SCGC1,3 ; SPI1 clock gate controlSPI0 cfbit SIM_SCGC1,2 ; SPI0 clock gate controlUART1 cfbit SIM_SCGC1,1 ; UART1 clock gate controlUART0 cfbit SIM_SCGC1,0 ; UART0 clock gate controlSIM_SCGC2 equ MBAR_SIM+$13 ; Clock Gate Control Register 2 (8b)CMP cfbit SIM_SCGC2,6 ; CMP clock gate controlTSI cfbit SIM_SCGC2,5 ; TSI clock gate controlVREF cfbit SIM_SCGC2,4 ; VREF clock gate controlADC cfbit SIM_SCGC2,1 ; ADC clock gate controlDAC12B cfbit SIM_SCGC2,0 ; 12-bit DAC clock gate controlSIM_SCGC3 equ MBAR_SIM+$14 ; Clock Gate Control Register 3 (8b)CRC cfbit SIM_SCGC3,7 ; CRC clock gate controlPDB cfbit SIM_SCGC3,6 ; PDB clock gate controlCMT cfbit SIM_SCGC3,5 ; CMT clock gate controlMTIM cfbit SIM_SCGC3,4 ; MTIM clock gate controlFTM1 cfbit SIM_SCGC3,3 ; FTM1 clock gate controlFTM0 cfbit SIM_SCGC3,2 ; FTM0 clock gate controlSIM_SCGC4 equ MBAR_SIM+$15 ; Clock Gate Control Register 4 (8b)FTFL cfbit SIM_SCGC4,7 ; FTFL clock gate controlDMA cfbit SIM_SCGC4,3 ; DMA clock gate controlIRQ cfbit SIM_SCGC4,1 ; IRQ clock gate controlWDOG cfbit SIM_SCGC4,0 ; COP clock gate controlSIM_SCGC5 equ MBAR_SIM+$16 ; Clock Gate Control Register 5 (8b)RNGB cfbit SIM_SCGC5,7 ; RNGB clock gate controlMFBUS cfbit SIM_SCGC5,6 ; MFBUS clock gate controlOSC2 cfbit SIM_SCGC5,2 ; OSC2 clock gate controlOSC1 cfbit SIM_SCGC5,1 ; OSC1 clock gate controlMCG cfbit SIM_SCGC5,0 ; MCG clock gate controlSIM_SCGC6 equ MBAR_SIM+$17 ; Clock Gate Control Register 6 (8b)PORTF cfbit SIM_SCGC6,5 ; Port F clock gate controlPORTE cfbit SIM_SCGC6,4 ; Port E clock gate controlPORTD cfbit SIM_SCGC6,3 ; Port D clock gate controlPORTC cfbit SIM_SCGC6,2 ; Port C clock gate controlPORTB cfbit SIM_SCGC6,1 ; Port B clock gate controlPORTA cfbit SIM_SCGC6,0 ; Port A clock gate controlSIM_CLKOUT equ MBAR_SIM+$1A ; Clockout Register (8b)CS cffield SIM_CLKOUT,4,3 ; CLKOUT pin clock selectCLKOUTDIV cffield SIM_CLKOUT,0,3 ; Division of the CLKOUT pinSIM_CLKDIV0 equ MBAR_SIM+$1B ; Clock Divider 0 Register (8b)OUTDIV cffield SIM_CLKDIV0,0,3 ; Clock output divider value to generate CPU clockSIM_SPCR equ MBAR_SIM+$20 ; Flash Configuration Register (8b)NVMSIZE cffield SIM_SPCR,4,4 ; FlexNVM sizePFSIZE cffield SIM_SPCR,0,4 ; Program flash sizeSIM_UIDH3 equ MBAR_SIM+$24 ; Unique Identification Register (8b)SIM_UIDH2 equ MBAR_SIM+$25 ; Unique Identification Register (8b)SIM_UIDH1 equ MBAR_SIM+$26 ; Unique Identification Register (8b)SIM_UIDH0 equ MBAR_SIM+$27 ; Unique Identification Register (8b)SIM_UIDMH3 equ MBAR_SIM+$28 ; Unique Identification Register (8b)SIM_UIDMH2 equ MBAR_SIM+$29 ; Unique Identification Register (8b)SIM_UIDMH1 equ MBAR_SIM+$2A ; Unique Identification Register (8b)SIM_UIDMH0 equ MBAR_SIM+$2B ; Unique Identification Register (8b)SIM_UIDML3 equ MBAR_SIM+$2C ; Unique Identification Register (8b)SIM_UIDML2 equ MBAR_SIM+$2D ; Unique Identification Register (8b)SIM_UIDML1 equ MBAR_SIM+$2E ; Unique Identification Register (8b)SIM_UIDML0 equ MBAR_SIM+$2F ; Unique Identification Register (8b)SIM_UIDL3 equ MBAR_SIM+$30 ; Unique Identification Register (8b)SIM_UIDL2 equ MBAR_SIM+$31 ; Unique Identification Register (8b)SIM_UIDL1 equ MBAR_SIM+$32 ; Unique Identification Register (8b)SIM_UIDL0 equ MBAR_SIM+$33 ; Unique Identification Register (8b);----------------------------------------------------------------------------; Power Management ControllerMBAR_PCM equ MBAR+$0100PMC_LVDSC1 equ MBAR_PCM+$00 ; Low Voltage Detect Status And Control 1 register (8b)LVDF cfbit PMC_LVDSC1,7 ; Low-Voltage Detect FlagLVDACK cfbit PMC_LVDSC1,6 ; Low-Voltage Detect AcknowledgeLVDIE cfbit PMC_LVDSC1,5 ; Low-Voltage Detect Interrupt EnableLVDRE cfbit PMC_LVDSC1,4 ; Low-Voltage Detect Reset EnableLVDV cffield PMC_LVDSC1,0,2 ; Low-Voltage Detect Voltage SelectPMC_LVDSC2 equ MBAR_PCM+$01 ; Low Voltage Detect Status And Control 2 register (8b)LVWF cfbit PMC_LVDSC2,7 ; Low-Voltage Warning FlagLVWACK cfbit PMC_LVDSC2,6 ; Low-Voltage Warning AcknowledgeLVWIE cfbit PMC_LVDSC2,5 ; Low-Voltage Warning Interrupt EnableLVWV cffield PMC_LVDSC2,0,2 ; Low-Voltage Warning Voltage SelectPMC_REGSC equ MBAR_PCM+$02 ; Regulator Status And Control register (8b)ACKISO cfbit PMC_REGSC,3 ; Acknowledge IsolationREGONS cfbit PMC_REGSC,2 ; Regulator In Run Regulation StatusBGBE cfbit PMC_REGSC,0 ; Bandgap Buffer Enable;----------------------------------------------------------------------------; Reset Control ModuleMBAR_RCM equ MBAR+$0110RCM_SRS0 equ MBAR_RCM+$00 ; System Reset Status Register 0 (8b)POR cfbit RCM_SRS0,7 ; Power-On ResetPIN cfbit RCM_SRS0,6 ; External Reset PinWDOG cfbit RCM_SRS0,5 ; WatchdogILOP cfbit RCM_SRS0,4 ; Illegal opcodeILAD cfbit RCM_SRS0,3 ; Illegal addressLOC cfbit RCM_SRS0,2 ; Loss-of-Clock ResetLVD cfbit RCM_SRS0,1 ; Low-Voltage Detect ResetWAKEUP cfbit RCM_SRS0,0 ; Low Leakage Wakeup ResetRCM_SRS1 equ MBAR_RCM+$01 ; System Reset Status Register 1 (8b)SACKERR cfbit RCM_SRS1,5 ; Stop Mode Acknowledge Error ResetEZPT cfbit RCM_SRS1,4 ; EzPort ResetBDFR cfbit RCM_SRS1,3 ; Background Debug Force ResetRCM_RPFC equ MBAR_RCM+$04 ; Reset Pin Filter Control register (8b)RSTFLTSS cfbit RCM_RPFC,2 ; Reset Pin Filter Select in Stop ModeRSTFLTSRW cffield RCM_RPFC,0,2 ; Reset Pin Filter Select in Run and Wait ModesRCM_RPFW equ MBAR_RCM+$05 ; Reset Pin Filter Width register (8b)RSTFLTSEL cffield RCM_RPFW,0,5 ; Reset Pin Filter Bus Clock SelectRCM_MR equ MBAR_RCM+$07 ; Mode Register (RCM_MR) (8b)EZP_MS cfbit RCM_MR,1 ; EZP_MS_B pin stateMS cfbit RCM_MR,0 ; MS_B Pin State;----------------------------------------------------------------------------; System Mode ControllerMBAR_SMC equ MBAR+$0118SMC_PMPROT equ MBAR_SMC+$00 ; Power Mode Protection register (8b)AVLP cfbit SMC_PMPROT,5 ; Allow Very-Low-Power ModesALLS cfbit SMC_PMPROT,3 ; Allow Low-Leakage Stop ModeAVLLS cfbit SMC_PMPROT,1 ; Allow Very-Low-Leakage Stop ModeSMC_PMCTRL equ MBAR_SMC+$01 ; Power Mode Control register (8b)LPWUI cfbit SMC_PMCTRL,7 ; Low-Power Wake Up On InterruptRUNM cffield SMC_PMCTRL,5,2 ; Run Mode ControlSTOPA cfbit SMC_PMCTRL,3 ; Stop AbortedSTOPM cffield SMC_PMCTRL,0,3 ; Stop Mode ControlSMC_VLLSCTRL equ MBAR_SMC+$02 ; VLLS Control register (8b)RAM2PO cfbit SMC_VLLSCTRL,4 ; RAM2 Power OptionVLLSM cffield SMC_VLLSCTRL,0,3 ; VLLS Mode ControlSMC_PMSTAT equ MBAR_SMC+$03 ; Power Mode Status register (8b)PMSTAT cffield SMC_PMSTAT,0,7 ; Current power mode;----------------------------------------------------------------------------; OSC Control Register__defosc macro NUM,BaseOSC{NUM}_CR equ Base+0 ; OSC Control Register (8b)ERCLKEN cfbit OSC{NUM}_CR,7 ; External Reference EnableEREFSTEN cfbit OSC{NUM}_CR,5 ; External Reference Stop EnableSC2P cfbit OSC{NUM}_CR,3 ; Oscillator 2 pF Capacitor Load ConfigureSC4P cfbit OSC{NUM}_CR,2 ; Oscillator 4 pF Capacitor Load ConfigureSC8P cfbit OSC{NUM}_CR,1 ; Oscillator 8 pF Capacitor Load ConfigureSC16P cfbit OSC{NUM}_CR,0 ; Oscillator 16 pF Capacitor Load ConfigureOSC{NUM}_TSTCTR equ Base+1 ; OSC Test Control Register (8b)OSCEN cfbit OSC{NUM}_TSTCTR,3 ; OSC Enable in Test ModeTSTEN cfbit OSC{NUM}_TSTCTR,2 ; VLP OSC Test EnableALCTST cfbit OSC{NUM}_TSTCTR,1 ; Auto Loop Control Test EnableCMPM cfbit OSC{NUM}_TSTCTR,0 ; AC-Coupling Comparator Operation Modeendm__defosc "1",MBAR+$0120__defosc "2",MBAR+$0130;----------------------------------------------------------------------------; Universal Asynchronous Receiver/Transmitter (with FIFO)__defuart macro NUM,BaseUART{NUM}_BDH equ Base+$00 ; UART Baud Rate Registers: High (8b)LBKDIE cfbit UART{NUM}_BDH,7 ; LIN Break Detect Interrupt EnableRXEDGIE cfbit UART{NUM}_BDH,6 ; RxD Input Active Edge Interrupt EnableSBR cffield UART{NUM}_BDH,0,5 ; UART Baud Rate BitsUART{NUM}_BDL equ Base+$01 ; UART Baud Rate Registers: Low (8b)SBR cffield UART{NUM}_BDL,0,8 ; UART Baud Rate BitsUART{NUM}_C1 equ Base+$02 ; UART Control Register 1 (8b)LOOPS cfbit UART{NUM}_C1,7 ; Loop Mode SelectUARTSWAI cfbit UART{NUM}_C1,6 ; UART Stops in Wait ModeRSRC cfbit UART{NUM}_C1,5 ; Receiver Source SelectM cfbit UART{NUM}_C1,4 ; 9-bit or 8-bit Mode SelectWAKE cfbit UART{NUM}_C1,3 ; Receiver Wakeup Method SelectILT cfbit UART{NUM}_C1,2 ; Idle Line Type SelectPE cfbit UART{NUM}_C1,1 ; Parity EnablePT cfbit UART{NUM}_C1,0 ; Parity TypeUART{NUM}_C2 equ Base+$03 ; UART Control Register 2 (8b)TIE cfbit UART{NUM}_C2,7 ; Transmitter Interrupt or DMA Transfer EnableTCIE cfbit UART{NUM}_C2,6 ; Transmission Complete Interrupt EnableRIE cfbit UART{NUM}_C2,5 ; Receiver Full Interrupt or DMA Transfer EnableILIE cfbit UART{NUM}_C2,4 ; Idle Line Interrupt EnableTE cfbit UART{NUM}_C2,3 ; Transmitter EnableRE cfbit UART{NUM}_C2,2 ; Receiver EnableRWU cfbit UART{NUM}_C2,1 ; Receiver Wakeup ControlSBK cfbit UART{NUM}_C2,0 ; Send BreakUART{NUM}_S1 equ Base+$04 ; UART Status Register 1 (8b)TDRE cfbit UART{NUM}_S1,7 ; Transmit Data Register Empty FlagTC cfbit UART{NUM}_S1,6 ; Transmit Complete FlagRDRF cfbit UART{NUM}_S1,5 ; Receive Data Register Full FlagIDLE cfbit UART{NUM}_S1,4 ; Idle Line FlagOR cfbit UART{NUM}_S1,3 ; Receiver Overrun FlagNF cfbit UART{NUM}_S1,2 ; Noise FlagFE cfbit UART{NUM}_S1,1 ; Framing Error FlagPF cfbit UART{NUM}_S1,0 ; Parity Error FlagUART{NUM}_S2 equ Base+$05 ; UART Status Register 2 (8b)LBKDIF cfbit UART{NUM}_S2,7 ; LIN Break Detect Interrupt FlagRXEDGIF cfbit UART{NUM}_S2,6 ; RxD Pin Active Edge Interrupt FlagMSBF cfbit UART{NUM}_S2,5 ; Most Significant Bit FirstRXINV cfbit UART{NUM}_S2,4 ; Receive Data InversionRWUID cfbit UART{NUM}_S2,3 ; Receive Wakeup Idle DetectBRK13 cfbit UART{NUM}_S2,2 ; Break Transmit Character LengthLBKDE cfbit UART{NUM}_S2,1 ; LIN Break Detection EnableRAF cfbit UART{NUM}_S2,0 ; Receiver Active FlagUART{NUM}_C3 equ Base+$06 ; UART Control Register 3 (8b)R8 cfbit UART{NUM}_C3,7 ; Received Bit 8T8 cfbit UART{NUM}_C3,6 ; Transmit Bit 8TXDIR cfbit UART{NUM}_C3,5 ; Transmitter Pin Data Direction in Single-Wire modeTXINV cfbit UART{NUM}_C3,4 ; Transmit Data InversionORIE cfbit UART{NUM}_C3,3 ; Overrun Error Interrupt EnableNEIE cfbit UART{NUM}_C3,2 ; Noise Error Interrupt EnableFEIE cfbit UART{NUM}_C3,1 ; Framing Error Interrupt EnablePEIE cfbit UART{NUM}_C3,0 ; Parity Error Interrupt EnableUART{NUM}_D equ Base+$07 ; UART Data Register (8b)RT cffield UART{NUM}_D,0,8 ; DataUART{NUM}_MA1 equ Base+$08 ; UART Match Address Registers 1 (8b)MA cffield UART{NUM}_MA1,0,8 ; Match AddressUART{NUM}_MA2 equ Base+$09 ; UART Match Address Registers 2 (8b)MA cffield UART{NUM}_MA2,0,8 ; Match AddressUART{NUM}_C4 equ Base+$0A ; UART Control Register 4 (8b)MAEN1 cfbit UART{NUM}_C4,7 ; Match Address Mode Enable 1MAEN2 cfbit UART{NUM}_C4,6 ; Match Address Mode Enable 2M10 cfbit UART{NUM}_C4,5 ; 10-bit Mode selectBRFA cffield UART{NUM}_C4,0,5 ; Baud Rate Fine AdjustUART{NUM}_C5 equ Base+$0B ; UART Control Register 5 (8b)TDMAS cfbit UART{NUM}_C5,7 ; Transmitter DMA SelectRDMAS cfbit UART{NUM}_C5,5 ; Receiver Full DMA SelectUART{NUM}_ED equ Base+$0C ; UART Extended Data Register (8b)NOISY cfbit UART{NUM}_ED,7 ; The current received dataword contained in D and C3[R8] was received with noisePARITYE cfbit UART{NUM}_ED,6 ; The current received dataword contained in D and C3[R8] was received with a parity errorUART{NUM}_MODEM equ Base+$0D ; UART Modem Register (8b)RXRTSE cfbit UART{NUM}_MODEM,3 ; Receiver request-to-send enableTXRTSPOL cfbit UART{NUM}_MODEM,2 ; Transmitter request-to-send polarityTXRTSE cfbit UART{NUM}_MODEM,1 ; Transmitter request-to-send enableTXCTSE cfbit UART{NUM}_MODEM,0 ; Transmitter clear-to-send enableUART{NUM}_PFIFO equ Base+$10 ; UART FIFO Parameters (8b)TXFE cfbit UART{NUM}_PFIFO,7 ; Transmit FIFO EnableTXFIFOSIZE cffield UART{NUM}_PFIFO,4,3 ; Transmit FIFO Buffer DepthRXFE cfbit UART{NUM}_PFIFO,3 ; Receive FIFO EnableRXFIFOSIZE cffield UART{NUM}_PFIFO,0,3 ; Receive FIFO Buffer DepthUART{NUM}_CFIFO equ Base+$11 ; UART FIFO Control Register (8b)TXFLUSH cfbit UART{NUM}_CFIFO,7 ; Transmit FIFO/Buffer FlushRXFLUSH cfbit UART{NUM}_CFIFO,6 ; Receive FIFO/Buffer FlushRXOFE cfbit UART{NUM}_CFIFO,2 ; Receive FIFO Overflow Interrupt EnableTXOFE cfbit UART{NUM}_CFIFO,1 ; Transmit FIFO Overflow Interrupt EnableRXUFE cfbit UART{NUM}_CFIFO,0 ; Receive FIFO Underflow Interrupt EnableUART{NUM}_SFIFO equ Base+$12 ; UART FIFO Status Register (8b)TXEMPT cfbit UART{NUM}_SFIFO,7 ; Transmit Buffer/FIFO EmptyRXEMPT cfbit UART{NUM}_SFIFO,6 ; Receive Buffer/FIFO EmptyRXOF cfbit UART{NUM}_SFIFO,2 ; Receiver Buffer Overflow FlagTXOF cfbit UART{NUM}_SFIFO,1 ; Transmitter Buffer Overflow FlagRXUF cfbit UART{NUM}_SFIFO,0 ; Receiver Buffer Underflow FlagUART{NUM}_TWFIFO equ Base+$13 ; UART FIFO Transmit Watermark (8b)TXWATER cffield UART{NUM}_TWFIFO,0,8 ; Transmit WatermarkUART{NUM}_TCFIFO equ Base+$14 ; UART FIFO Transmit Count (8b)TXCOUNT cffield UART{NUM}_TCFIFO,0,8 ; Transmit CounterUART{NUM}_RWFIFO equ Base+$15 ; UART FIFO Receive Watermark (8b)RXWATER cffield UART{NUM}_RWFIFO,0,8 ; Receive WatermarkUART{NUM}_RCFIFO equ Base+$16 ; UART FIFO Receive Count (8b)RXCOUNT cffield UART{NUM}_RCFIFO,0,8 ; Receive CounterUART{NUM}_C7816 equ Base+$18 ; UART 7816 Control Register (8b)ONACK cfbit UART{NUM}_C7816,4 ; Generate NACK on OverflowANACK cfbit UART{NUM}_C7816,3 ; Generate NACK on ErrorINIT cfbit UART{NUM}_C7816,2 ; Detect Initial CharacterTTYPE cfbit UART{NUM}_C7816,1 ; Transfer TypeISO_7816E cfbit UART{NUM}_C7816,0 ; ISO-7816 Functionality EnabledUART{NUM}_IE7816 equ Base+$19 ; UART 7816 Interrupt Enable Register (8b)WTE cfbit UART{NUM}_IE7816,7 ; Wait Timer Interrupt EnableCWTE cfbit UART{NUM}_IE7816,6 ; Character Wait Timer Interrupt EnableBWTE cfbit UART{NUM}_IE7816,5 ; Block Wait Timer Interrupt EnableINITDE cfbit UART{NUM}_IE7816,4 ; Initial Character Detected Interrupt EnableGTVE cfbit UART{NUM}_IE7816,2 ; Guard Timer Violated Interrupt EnableTXTE cfbit UART{NUM}_IE7816,1 ; Transmit Threshold Exceeded Interrupt EnableRXTE cfbit UART{NUM}_IE7816,0 ; Receive Threshold Exceeded Interrupt EnableUART{NUM}_IS7816 equ Base+$1A ; UART 7816 Interrupt Status Register (8b)WT cfbit UART{NUM}_IS7816,7 ; Wait Timer InterruptCWT cfbit UART{NUM}_IS7816,6 ; Character Wait Timer InterruptBWT cfbit UART{NUM}_IS7816,5 ; Block Wait Timer InterruptINITD cfbit UART{NUM}_IS7816,4 ; Initial Character Detected InterruptGTV cfbit UART{NUM}_IS7816,2 ; Guard Timer Violated InterruptTXT cfbit UART{NUM}_IS7816,1 ; Transmit Threshold Exceeded InterruptRXT cfbit UART{NUM}_IS7816,0 ; Receive Threshold Exceeded InterruptUART{NUM}_WP7816T0 equ Base+$1B ; UART 7816 Wait Parameter Register (8b)WI cffield UART{NUM}_WP7816T0,0,8 ; Wait Timer InterruptUART{NUM}_WP7816T1 equ Base+$1B ; UART 7816 Wait Parameter Register (8b)CWI cffield UART{NUM}_WP7816T1,4,4 ; Character Wait Time IntegerBWI cffield UART{NUM}_WP7816T1,0,4 ; Block Wait Time IntegerUART{NUM}_WN7816 equ Base+$1C ; UART 7816 Wait N Register (8b)GTN cffield UART{NUM}_WN7816,0,8 ; Guard Band NUART{NUM}_WF7816 equ Base+$1D ; UART 7816 Wait FD Register (8b)GTFD cffield UART{NUM}_WF7816,0,8 ; FD MultiplierUART{NUM}_ET7816 equ Base+$1E ; UART 7816 Error Threshold Register (8b)TXTHRESHOLD cffield UART{NUM}_ET7816,4,4 ; Transmit NACK ThresholdRXTHRESHOLD cffield UART{NUM}_ET7816,0,4 ; Receive NACK ThresholdUART{NUM}_TL7816 equ Base+$1F ; UART 7816 Transmit Length Register (8b)TLEN cffield UART{NUM}_TL7816,0,8 ; Transmit Lengthendm__defuart "0",MBAR+$0140__defuart "1",MBAR+$0160;----------------------------------------------------------------------------; Serial Peripheral Interface (with FIFO)__defspi macro NUM,BaseSPI{NUM}_C1 equ Base+$00 ; SPI control register 1 (8b)SPIE cfbit SPI{NUM}_C1,7 ; SPI interrupt enableSPE cfbit SPI{NUM}_C1,6 ; SPI system enableSPTIE cfbit SPI{NUM}_C1,5 ; SPI transmit interrupt enableMSTR cfbit SPI{NUM}_C1,4 ; Master/slave mode selectCPOL cfbit SPI{NUM}_C1,3 ; Clock polarityCPHA cfbit SPI{NUM}_C1,2 ; Clock phaseSSOE cfbit SPI{NUM}_C1,1 ; Slave select output enableLSBFE cfbit SPI{NUM}_C1,0 ; LSB first (shifter directionSPI{NUM}_C2 equ Base+$01 ; SPI control register 2 (8b)SPMIE cfbit SPI{NUM}_C2,7 ; SPI match interrupt enableSPIMODE cfbit SPI{NUM}_C2,6 ; SPI 8-bit or 16-bit modeTXDMAE cfbit SPI{NUM}_C2,5 ; Transmit DMA enableMODFEN cfbit SPI{NUM}_C2,4 ; Master mode-fault function enableBIDIROE cfbit SPI{NUM}_C2,3 ; Bidirectional mode output enableRXDMAE cfbit SPI{NUM}_C2,2 ; Receive DMA enableSPISWAI cfbit SPI{NUM}_C2,1 ; SPI stop in wait modeSPC0 cfbit SPI{NUM}_C2,0 ; SPI pin control 0SPI{NUM}_BR equ Base+$02 ; SPI baud rate register (8b)SPPR cffield SPI{NUM}_BR,4,3 ; SPI baud rate prescale divisorSPR cffield SPI{NUM}_BR,0,4 ; SPI baud rate divisorSPI{NUM}_S equ Base+$03 ; SPI status register (8b)SPRF cfbit SPI{NUM}_S,7 ; SPI read buffer full flagSPMF cfbit SPI{NUM}_S,6 ; SPI match flagSPTEF cfbit SPI{NUM}_S,5 ; SPI transmit buffer empty flagMODF cfbit SPI{NUM}_S,4 ; Master mode fault flagSPI{NUM}_DH equ Base+$04 ; SPI data register high (8b)SPI{NUM}_DL equ Base+$05 ; SPI data register low (8b)SPI{NUM}_MH equ Base+$06 ; SPI match register high (8b)SPI{NUM}_ML equ Base+$07 ; SPI match register low (8b)endmMBAR_SPI0 equ MBAR+$01a0__defspi "0",MBAR_SPI0RNFULLF cfbit SPI0_S,3 ; Receive FIFO nearly full flagTNEAREF cfbit SPI0_S,2 ; Transmit FIFO nearly empty flagTXFULLF cfbit SPI0_S,1 ; Transmit FIFO full flagRFIFOEF cfbit SPI0_S,0 ; SPI read FIFO empty flagSPI0_C3 equ MBAR_SPI0+$08 ; SPI0 control register 3TNEAREF_MARK cfbit SPI0_C3,5 ; Transmit FIFO nearly empty watermarkRNFULLF_MARK cfbit SPI0_C3,4 ; Receive FIFO nearly full watermarkINTCLR cfbit SPI0_C3,3 ; Interrupt clearing mechanism selectTNEARIEN cfbit SPI0_C3,2 ; Transmit FIFO nearly empty interrupt enableRNFULLIEN cfbit SPI0_C3,1 ; Receive FIFO nearly full interrupt enableFIFOMODE cfbit SPI0_C3,0 ; FIFO mode enableSPI0_CI equ MBAR_SPI0+$09 ; SPI0 clear interrupt registerTXFERR cfbit SPI0_CI,7 ; Transmit FIFO error flagRXFERR cfbit SPI0_CI,6 ; Receive FIFO error flagTXFOF cfbit SPI0_CI,5 ; Transmit FIFO overflow flagRXFOF cfbit SPI0_CI,4 ; Receive FIFO overflow flagTNEAREFCI cfbit SPI0_CI,3 ; Transmit FIFO nearly empty flag clear interruptRNFULLFCI cfbit SPI0_CI,2 ; Receive FIFO nearly full flag clear interruptSPTEFCI cfbit SPI0_CI,1 ; Transmit FIFO empty flag clear interruptSPRFCI cfbit SPI0_CI,0 ; Receive FIFO full flag clear interrupt;----------------------------------------------------------------------------; Serial Peripheral Interface (without FIFO)MBAR_SPI1 equ MBAR+$01b0__defspi "1",MBAR_SPI1;----------------------------------------------------------------------------; Inter-Integrated IC__defi2c macro NUM,BaseI2C{NUM}_A1 equ Base+$00 ; I2C Address Register 1 (8b)AD cffield I2C{NUM}_A1,1,7 ; AddressI2C{NUM}_F equ Base+$01 ; I2C Frequency Divider register (8b)MULT cffield I2C{NUM}_F,6,2 ; The MULT bits define the multiplier factor mulICR cffield I2C{NUM}_F,0,6 ; ClockRateI2C{NUM}_C1 equ Base+$02 ; I2C Control Register 1 (8b)IICEN cfbit I2C{NUM}_C1,7 ; I2C EnableIICIE cfbit I2C{NUM}_C1,6 ; I2C Interrupt EnableMST cfbit I2C{NUM}_C1,5 ; Master Mode SelectTX cfbit I2C{NUM}_C1,4 ; Transmit Mode SelectTXAK cfbit I2C{NUM}_C1,3 ; Transmit Acknowledge EnableRSTA cfbit I2C{NUM}_C1,2 ; Repeat STARTWUEN cfbit I2C{NUM}_C1,1 ; Wakeup EnableDMAEN cfbit I2C{NUM}_C1,0 ; DMA EnableI2C{NUM}_S equ Base+$03 ; I2C Status register (8b)TCF cfbit I2C{NUM}_S,7 ; Transfer Complete FlagIAAS cfbit I2C{NUM}_S,6 ; Addressed As A SlaveBUSY cfbit I2C{NUM}_S,5 ; Bus BusyARBL cfbit I2C{NUM}_S,4 ; Arbitration LostRAM cfbit I2C{NUM}_S,3 ; Range Address MatchSRW cfbit I2C{NUM}_S,2 ; Slave Read/WriteIICIF cfbit I2C{NUM}_S,1 ; Interrupt FlagRXAK cfbit I2C{NUM}_S,0 ; Receive AcknowledgeI2C{NUM}_D equ Base+$04 ; I2C Data I/O register (8b)DATA cffield I2C{NUM}_D,0,8 ; DataI2C{NUM}_C2 equ Base+$05 ; I2C Control Register 2 (8b)GCAEN cfbit I2C{NUM}_C2,7 ; General Call Address EnableADEXT cfbit I2C{NUM}_C2,6 ; Address ExtensionHDRS cfbit I2C{NUM}_C2,5 ; High Drive SelectSBRC cfbit I2C{NUM}_C2,4 ; Slave Baud Rate ControlRMEN cfbit I2C{NUM}_C2,3 ; Range Address Matching EnableAD cffield I2C{NUM}_C2,0,3 ; Slave AddressI2C{NUM}_FLT equ Base+$06 ; I2C Programmable Input Glitch Filter register (8b)FLT cffield I2C{NUM}_FLT,0,4 ; I2C Programmable Filter FactorI2C{NUM}_RA equ Base+$07 ; I2C Range Address register (8b)RAD cffield I2C{NUM}_RA,1,7 ; Range Slave AddressI2C{NUM}_SMB equ Base+$08 ; I2C SMBus Control and Status register (8b)FACK cfbit I2C{NUM}_SMB,7 ; Fast NACK/ACK EnableALERTEN cfbit I2C{NUM}_SMB,6 ; SMBus Alert Response Address EnableSIICAEN cfbit I2C{NUM}_SMB,5 ; Second I2C Address EnableTCKSEL cfbit I2C{NUM}_SMB,4 ; Timeout Counter Clock SelectSLTF cfbit I2C{NUM}_SMB,3 ; SCL Low Timeout FlagSHTF1 cfbit I2C{NUM}_SMB,2 ; SCL High Timeout Flag 1SHTF2 cfbit I2C{NUM}_SMB,1 ; SCL High Timeout Flag 2SHTF2IE cfbit I2C{NUM}_SMB,0 ; SHTF2 Interrupt EnableI2C{NUM}_A2 equ Base+$09 ; I2C Address Register 2 (8b)SAD cffield I2C{NUM}_A2,1,7 ; SMBus AddressI2C{NUM}_SLT equ Base+$0ASSLT cffield I2C{NUM}_SLT,0,16 ; SCL low timeout value that determines the timeout period of SCL lowI2C{NUM}_SLTH equ Base+$0A ; I2C SCL Low Timeout Register High (8b)I2C{NUM}_SLTL equ Base+$0B ; I2C SCL Low Timeout Register Low (8b)endm__defi2c "0",MBAR+$01c0__defi2c "1",MBAR+$01d0__defi2c "2",MBAR+$01e0__defi2c "3",MBAR+$01f0;----------------------------------------------------------------------------; Multipurpose Clock GeneratorMBAR_MCG equ MBAR+$0400MCG_C1 equ MBAR_MCG+$00 ; MCG Control 1 Register (8b)CLKS cffield MCG_C1,6,2 ; Clock Source SelectFRDIV cffield MCG_C1,3,3 ; FLL External Reference DividerIREFS cfbit MCG_C1,2 ; Internal Reference SelectIRCLKEN cfbit MCG_C1,1 ; Internal Reference Clock EnableIREFSTEN cfbit MCG_C1,0 ; Internal Reference Stop EnableMCG_C2 equ MBAR_MCG+$01 ; MCG Control 2 Register (8b)RANGE cffield MCG_C2,4,2 ; Frequency Range SelectHGO cfbit MCG_C2,3 ; High Gain Oscillator SelectEREFS cfbit MCG_C2,2 ; External Reference SelectLP cfbit MCG_C2,1 ; Low Power SelectIRCS cfbit MCG_C2,0 ; Internal Reference Clock SelectMCG_C3 equ MBAR_MCG+$02 ; MCG Control 3 Register (8b)SCTRIM cffield MCG_C3,0,8 ; Slow Internal Reference Clock Trim SettingMCG_C4 equ MBAR_MCG+$03 ; MCG Control 4 Register (8b)DMX32 cfbit MCG_C4,7 ; DCO Maximum Frequency with 32.768 kHz ReferenceDRST_DRS cffield MCG_C4,5,2 ; DCO Range SelectFCTRIM cffield MCG_C4,1,4 ; Fast Internal Reference Clock Trim SettingSCFTRIM cfbit MCG_C4,0 ; Slow Internal Reference Clock Fine TrimMCG_C5 equ MBAR_MCG+$04 ; MCG Control 5 Register (8b)PLLCLKEN cfbit MCG_C5,6 ; PLL Clock EnablePLLSTEN cfbit MCG_C5,5 ; PLL Stop EnablePRDIV cffield MCG_C5,0,5 ; PLL External Reference DividerMCG_C6 equ MBAR_MCG+$05 ; MCG Control 6 Register (8b)LOLIE cfbit MCG_C6,7 ; Loss of Lock Interrrupt EnablePLLS cfbit MCG_C6,6 ; PLL SelectCME cfbit MCG_C6,5 ; Clock Monitor EnableVDIV cffield MCG_C6,0,5 ; VCO DividerMCG_S equ MBAR_MCG+$06 ; MCG Status Register (8b)LOLS cfbit MCG_S,7 ; Loss of Lock StatusLOCK0 cfbit MCG_S,6 ; Lock StatusPLLST cfbit MCG_S,5 ; PLL Select StatusIREFST cfbit MCG_S,4 ; Internal Reference StatusCLKST cffield MCG_S,2,2 ; Clock Mode StatusOSCINIT cfbit MCG_S,1 ; OSC InitializationIRCST cfbit MCG_S,0 ; Internal Reference Clock StatusMCG_ATC equ MBAR_MCG+$08 ; MCG Auto Trim Control Register (8b)ATME cfbit MCG_ATC,7 ; Automatic Trim Machine EnableATMS cfbit MCG_ATC,6 ; Automatic Trim Machine SelectATMF cfbit MCG_ATC,5 ; Automatic Trim machine Fail FlagMCG_ATCVH equ MBAR_MCG+$0A ; MCG Auto Trim Compare Value High Register (8b)ATCVH cffield MCG_ATCVH,0,8 ; ATM Compare Value HighMCG_ATCVL equ MBAR_MCG+$0B ; MCG Auto Trim Compare Value Low Register (8b)ATCVL cffield MCG_ATCVL,0,8 ; ATM Compare Value Low;----------------------------------------------------------------------------; 16-Bit Modulo TimerMBAR_MTIM16 equ MBAR+$0410MTIM0_SC equ MBAR_MTIM16+$00 ; MTIM16 status and control register (8b)TOF cfbit MTIM0_SC,7 ; MTIM16 overflow flagTOIE cfbit MTIM0_SC,6 ; MTIM16 overflow interrupt enableTRST cfbit MTIM0_SC,5 ; MTIM16 counter resetTSTP cfbit MTIM0_SC,4 ; MTIM16 counter stopMTIM0_CLK equ MBAR_MTIM16+$01 ; MTIM16 clock configuration register (8b)CLKS cffield MTIM0_CLK,4,2 ; Clock source selectPS cffield MTIM0_CLK,0,4 ; Clock source prescalerMTIM0_CNTH equ MBAR_MTIM16+$02 ; MTIM16 counter register high (8b)CNTH cffield MTIM0_CNTH,0,8 ; MTIM16 count (high byte)MTIM0_CNTL equ MBAR_MTIM16+$03 ; MTIM16 counter register low (8b)CNTL cffield MTIM0_CNTL,0,8 ; MTIM16 count (low byte)MTIM0_MODH equ MBAR_MTIM16+$04 ; MTIM16 modulo register high (8b)MODH cffield MTIM0_MODH,0,8 ; MTIM16 modulo (high byte)MTIM0_MODL equ MBAR_MTIM16+$05 ; MTIM16 modulo register low (8b)MODL cffield MTIM0_MODL,0,8 ; MTIM16 modulo (low byte);----------------------------------------------------------------------------; Carrier Modulator TransmitterMBAR_CMT equ MBAR+$0420CMT_CGH1 equ MBAR_CMT+$00 ; CMT Carrier Generator High Data Register 1 (8b)PH cffield CMT_CGH1,0,8 ; Primary Carrier High Time Data ValueCMT_CGL1 equ MBAR_CMT+$01 ; CMT Carrier Generator Low Data Register 1 (8b)PL cffield CMT_CGL1,0,8 ; Primary Carrier Low Time Data ValueCMT_CGH2 equ MBAR_CMT+$02 ; CMT Carrier Generator High Data Register 2 (8b)SH cffield CMT_CGH2,0,8 ; Secondary Carrier High Time Data ValueCMT_CGL2 equ MBAR_CMT+$03 ; CMT Carrier Generator Low Data Register 2 (8b)SL cffield CMT_CGL2,0,8 ; Secondary Carrier Low Time Data ValueCMT_OC equ MBAR_CMT+$04 ; CMT Output Control Register (8b)IROL cfbit CMT_OC,7 ; IRO Latch ControlCMTPOL cfbit CMT_OC,6 ; CMT Output PolarityIROPEN cfbit CMT_OC,5 ; IRO Pin EnableCMT_MSC equ MBAR_CMT+$05 ; CMT Modulator Status and Control Register (8b)EOCF cfbit CMT_MSC,7 ; End Of Cycle Status FlagCMTDIV cffield CMT_MSC,5,2 ; CMT Clock Divide PrescalerEXSPC cfbit CMT_MSC,4 ; Extended Space EnableBASE cfbit CMT_MSC,3 ; Baseband EnableFSK cfbit CMT_MSC,2 ; FSK Mode SelectEOCIE cfbit CMT_MSC,1 ; End of Cycle Interrupt EnableMCGEN cfbit CMT_MSC,0 ; Modulator and Carrier Generator EnableCMT_CMD1 equ MBAR_CMT+$06 ; CMT Modulator Data Register Mark High (8b)CMT_CMD2 equ MBAR_CMT+$07 ; CMT Modulator Data Register Mark Low (8b)CMT_CMD3 equ MBAR_CMT+$08 ; CMT Modulator Data Register Space High (8b)CMT_CMD4 equ MBAR_CMT+$09 ; CMT Modulator Data Register Space Low (8b)CMT_PPS equ MBAR_CMT+$0A ; CMT Primary Prescaler Register (8b)PPSDIV cffield CMT_PPS,0,4 ; Primary Prescaler DividerCMT_DMA equ MBAR_CMT+$0B ; CMT Direct Memory Access Register (8b)DMA cfbit CMT_DMA,0,1 ; DMA Enable;----------------------------------------------------------------------------; 2-channel Flex Timer / PWM Module__deftimer macro NUM,Base,NumChansFTM{NUM}_SC equ Base+$00 ; Status and Control (8b)TOF cfbit FTM{NUM}_SC,7 ; Timer Overflow FlagTOIE cfbit FTM{NUM}_SC,6 ; Timer Overflow Interrupt EnableCPWMS cfbit FTM{NUM}_SC,5 ; Center-aligned PWM SelectCLKS cffield FTM{NUM}_SC,3,2 ; Clock Source SelectionPS cffield FTM{NUM}_SC,0,3 ; Prescale Factor SelectionFTM{NUM}_CNTH equ Base+$01 ; Counter High (8b)COUNT_H cffield FTM{NUM}_CNTH,0,8 ; Counter value high byteFTM{NUM}_CNTL equ Base+$02 ; Counter Low (8b)COUNT_L cffield FTM{NUM}_CNTL,0,8 ; Counter value low byteFTM{NUM}_MODH equ Base+$03 ; Modulo High (8b)MOD_H cffield FTM{NUM}_MODH,0,8 ; High byte of the modulo valueFTM{NUM}_MODL equ Base+$04 ; Modulo Low (8b)MOD_L cffield FTM{NUM}_MODL,0,8 ; Low byte of the modulo value__N set 0rept NumChans__decstr __NS,__NFTM{NUM}_C{__NS}SC equ Base+$05+(__N*3) ; Channel Status and Control (8b)CHF cfbit FTM{NUM}_C{__NS}SC,7 ; Channel FlagCHIE cfbit FTM{NUM}_C{__NS}SC,6 ; Channel Interrupt EnableMSB cfbit FTM{NUM}_C{__NS}SC,5 ; Channel Mode SelectMSA cfbit FTM{NUM}_C{__NS}SC,4 ; Channel Mode SelectELSB cfbit FTM{NUM}_C{__NS}SC,3 ; Edge or Level SelectELSA cfbit FTM{NUM}_C{__NS}SC,2 ; Edge or Level SelectDMA cfbit FTM{NUM}_C{__NS}SC,0 ; DMA EnableFTM{NUM}_C{__NS}VH equ Base+$06+(__N*3) ; Channel Value High (8b)VAL_H cffield FTM{NUM}_C{__NS}VH,0,8 ; Channel Value High ByteFTM{NUM}_C{__NS}VL equ Base+$07+(__N*3) ; Channel Value Low (8b)VAL_L cffield FTM{NUM}_C{__NS}VL,0,8 ; Channel Value Low Byte__N set __N+1endmFTM{NUM}_CNTINH equ Base+$20 ; Counter Initial Value High (8b)INIT_H cffield FTM{NUM}_CNTINH,0,8 ; Counter Initial Value High ByteFTM{NUM}_CNTINL equ Base+$21 ; Counter Initial Value Low (8)INIT_L cffield FTM{NUM}_CNTINL,0,8 ; Counter Initial Value Low ByteFTM{NUM}_STATUS equ Base+$22 ; Capture and Compare Status (8b)__enumbits2 FTM{NUM}_STATUS,CH,F,NumChansFTM{NUM}_MODE equ Base+$23 ; Features Mode Selection (8b)FAULTIE cfbit FTM{NUM}_MODE,7 ; Fault Interrupt EnableFAULTM cffield FTM{NUM}_MODE,5,2 ; Fault Control ModeCAPTEST cfbit FTM{NUM}_MODE,4 ; Capture Test Mode EnablePWMSYNC cfbit FTM{NUM}_MODE,3 ; PWM Synchronization ModeWPDIS cfbit FTM{NUM}_MODE,2 ; Write Protection DisableINIT cfbit FTM{NUM}_MODE,1 ; Initialize the Output ChannelsFTMEN cfbit FTM{NUM}_MODE,0 ; FTM EnableFTM{NUM}_SYNC equ Base+$24 ; Synchronization (8b)SWSYNC cfbit FTM{NUM}_SYNC,7 ; PWM Synchronization Software TriggerTRIG2 cfbit FTM{NUM}_SYNC,6 ; PWM Synchronization External Trigger 2TRIG1 cfbit FTM{NUM}_SYNC,5 ; PWM Synchronization External Trigger 1TRIG0 cfbit FTM{NUM}_SYNC,4 ; PWM Synchronization External Trigger 0SYNCHOM cfbit FTM{NUM}_SYNC,3 ; Output Mask SynchronizationREINIT cfbit FTM{NUM}_SYNC,2 ; FTM Counter Reinitialization by SynchronizationCNTMAX cfbit FTM{NUM}_SYNC,1 ; Maximum Boundary Cycle EnableCNTMIN cfbit FTM{NUM}_SYNC,0 ; Minimum Boundary Cycle EnableFTM{NUM}_OUTINIT equ Base+$25 ; Initial State for Channel Output (8b)__enumbits2 FTM{NUM}_OUTINIT,CH,OI,NumChansFTM{NUM}_OUTMASK equ Base+$26 ; Output Mask (8b)__enumbits2 FTM{NUM}_OUTMASK,CH,M,NumChansFTM{NUM}_COMBINE0 equ Base+$27 ; Function for Linked Channels (8b)FAULTEN cfbit FTM{NUM}_COMBINE0,6 ; Fault Control EnableSYNCEN cfbit FTM{NUM}_COMBINE0,5 ; Synchronization EnableDTEN cfbit FTM{NUM}_COMBINE0,4 ; Deadtime EnableDECAP cfbit FTM{NUM}_COMBINE0,3 ; Dual Edge Capture Mode CapturesDECAPEN cfbit FTM{NUM}_COMBINE0,2 ; Dual Edge Capture Mode EnableCOMP cfbit FTM{NUM}_COMBINE0,1 ; Complement of Channel (n)COMBINE cfbit FTM{NUM}_COMBINE0,0 ; Combine ChannelsFTM{NUM}_DEADTIME equ Base+$2B ; Deadtime Insertion Control (8b)DTPS cffield FTM{NUM}_DEADTIME,6,2 ; Deadtime Prescaler ValueDTVAL cffield FTM{NUM}_DEADTIME,0,6 ; Deadtime ValueFTM{NUM}_EXTTRIG equ Base+$2C ; External Trigger (8b)TRIGF cfbit FTM{NUM}_EXTTRIG,7 ; Channel Trigger FlagINITTRIGEN cfbit FTM{NUM}_EXTTRIG,6 ; Initialization Trigger EnableCH1TRIG cfbit FTM{NUM}_EXTTRIG,5 ; Channel 1 Trigger EnableCH0TRIG cfbit FTM{NUM}_EXTTRIG,4 ; Channel 0 Trigger Enable__enumbits2 FTM{NUM}_EXTTRIG,CH,TRIG,4,2FTM{NUM}_POL equ Base+$2D ; Channels Polarity (8b)__enumbits FTM{NUM}_POL,POL,NumChans ; Channel n PolarityFTM{NUM}_FMS equ Base+$2E ; Fault Mode Status (8b)FAULTF cfbit FTM{NUM}_FMS,7 ; Fault Detection FlagWPEN cfbit FTM{NUM}_FMS,6 ; Write Protection EnableFAULTIN cfbit FTM{NUM}_FMS,5 ; Fault InputsFAULTF3 cfbit FTM{NUM}_FMS,3 ; Fault Detection Flag 3FAULTF2 cfbit FTM{NUM}_FMS,2 ; Fault Detection Flag 2FAULTF1 cfbit FTM{NUM}_FMS,1 ; Fault Detection Flag 1FAULTF0 cfbit FTM{NUM}_FMS,0 ; Fault Detection Flag 0FTM{NUM}_FILTER0 equ Base+$2F ; Input Capture Filter Control (8b)CHoddFVAL cffield FTM{NUM}_FILTER0,4,4 ; Input Filter for Odd ChannelCHevenFVAL cffield FTM{NUM}_FILTER0,0,4 ; Input Filter for Even ChannelFTM{NUM}_FILTER1 equ Base+$30 ; Input Capture Filter Control (8b)CHoddFVAL cffield FTM{NUM}_FILTER1,4,4 ; Input Filter for Odd ChannelCHevenFVAL cffield FTM{NUM}_FILTER1,0,4 ; Input Filter for Even ChannelFTM{NUM}_FLTFILTER equ Base+$31 ; Fault Input Filter Control (8b)FFVAL cffield FTM{NUM}_FLTFILTER,0,4 ; Fault Input FilterFTM{NUM}_FLTCTRL equ Base+$32 ; Fault Input Control (8b)FFLTR3EN cfbit FTM{NUM}_FLTCTRL,7 ; Fault Input 3 Filter EnableFFLTR2EN cfbit FTM{NUM}_FLTCTRL,6 ; Fault Input 2 Filter EnableFFLTR1EN cfbit FTM{NUM}_FLTCTRL,5 ; Fault Input 1 Filter EnableFFLTR0EN cfbit FTM{NUM}_FLTCTRL,4 ; Fault Input 0 Filter Enable__enumbits2 FTM{NUM}_FLTCTRL,FAULT,EN,4 ; Fault Input n EnableFTM{NUM}_QDCTRL equ Base+$33 ; Quadrature Decoder Control and Status (8b)PHAFLTREN cfbit FTM{NUM}_QDCTRL,7 ; Phase A Input Filter EnablePHBFLTREN cfbit FTM{NUM}_QDCTRL,6 ; Phase B Input Filter EnablePHAPOL cfbit FTM{NUM}_QDCTRL,5 ; Phase A Input PolarityPHBPOL cfbit FTM{NUM}_QDCTRL,4 ; Phase B Input PolarityQUADMODE cfbit FTM{NUM}_QDCTRL,3 ; Quadrature Decoder ModeQUADIR cfbit FTM{NUM}_QDCTRL,2 ; FTM Counter Direction in Quadrature Decoder ModeTOFDIR cfbit FTM{NUM}_QDCTRL,1 ; Timer Overflow Direction in Quadrature Decoder ModeQUADEN cfbit FTM{NUM}_QDCTRL,0 ; Quadrature Decoder Mode EnableendmMBAR_FTM0 equ MBAR+$0440__deftimer "0",MBAR_FTM0,2;----------------------------------------------------------------------------; 6-channel Flex Timer / PWM ModuleMBAR_FTM1 equ MBAR+$0480__deftimer "1",MBAR_FTM1,6;----------------------------------------------------------------------------; Low Power Timer__deflptmr macro NUM,BaseLPTMR{NUM}_CSR equ Base+$00 ; Low Power Timer n Control Status Register (32b)TCF cfbit LPTMR{NUM}_CSR,7 ; Timer Compare FlagTIE cfbit LPTMR{NUM}_CSR,6 ; Timer Interrupt EnableTPS cffield LPTMR{NUM}_CSR,4,2 ; Timer Pin SelectTPP cfbit LPTMR{NUM}_CSR,3 ; Timer Pin PolarityTFC cfbit LPTMR{NUM}_CSR,2 ; Timer Free-Running CounterTMS cfbit LPTMR{NUM}_CSR,1 ; Timer Mode SelectTEN cfbit LPTMR{NUM}_CSR,0 ; Timer EnableLPTMR{NUM}_PSR equ Base+$04 ; Low Power Timer n Prescale Register (32b)PRESCALE cffield LPTMR{NUM}_PSR,3,4 ; Prescale ValuePBYP cfbit LPTMR{NUM}_PSR,2 ; Prescaler BypassPCS cffield LPTMR{NUM}_PSR,0,2 ; Prescaler Clock SelectLPTMR{NUM}_CMR equ Base+$08 ; Low Power Timer n Compare Register (32b)COMPARE cffield LPTMR{NUM}_CMR,0,16 ; Compare ValueLPTMR{NUM}_CNR equ Base+$0c ; Low Power Timer n Counter Register (32b)COUNTER cffield LPTMR{NUM}_CNR,0,16 ; Counter Valueendm__deflptmr "0",MBAR+$04c0__deflptmr "1",MBAR+$04d0;----------------------------------------------------------------------------; Flash ControllerMBAR_FTFL equ MBAR+$04e0FTFL_FOPT equ MBAR_FTFL+$00 ; Flash Option Register (8b)OPT cffield FTFL_FOPT,0,8 ; Nonvolatile OptionFTFL_FSEC equ MBAR_FTFL+$01 ; Flash Security Register (8b)KEYEN cffield FTFL_FSEC,6,2 ; Backdoor Key Security EnableMEEN cffield FTFL_FSEC,4,2 ; Mass Erase Enable BitsFSLACC cffield FTFL_FSEC,2,2 ; Freescale Failure Analysis Access CodeSEC cffield FTFL_FSEC,0,2 ; Flash SecurityFTFL_FCNFG equ MBAR_FTFL+$02 ; Flash Configuration Register (8b)CCIE cfbit FTFL_FCNFG,7 ; Command Complete Interrupt EnableRDCOLLIE cfbit FTFL_FCNFG,6 ; Read Collision Error Interrupt EnableERSAREQ cfbit FTFL_FCNFG,5 ; Erase All RequestERSSUSP cfbit FTFL_FCNFG,4 ; Erase SuspendPFLSH cfbit FTFL_FCNFG,2 ; Flash memory configurationRAMRDY cfbit FTFL_FCNFG,1 ; RAM ReadyEEERDY cfbit FTFL_FCNFG,0 ; indicates if the EEPROM backup data has been copied to the FlexRAMFTFL_FSTAT equ MBAR_FTFL+$03 ; Flash Status Register (8b)CCIF cfbit FTFL_FSTAT,7 ; Command Complete Interrupt FlagRDCOLERR cfbit FTFL_FSTAT,6 ; Flash Read Collision Error FlagACCERR cfbit FTFL_FSTAT,5 ; Flash Access Error FlagFPVIOL cfbit FTFL_FSTAT,4 ; Flash Protection Violation FlagMGSTAT0 cfbit FTFL_FSTAT,0 ; Memory Controller Command Completion Status Flag__N set 0rept 12__hexstr __NS,__NFTFL_FCCOB{__NS} equ MBAR_FTFL+$04+__N ; Flash Common Command Object Register n (8b)CCOB{__NS} cffield FTFL_FCCOB{__NS},0,8 ; command code/parameter__N set __N+1endm__N set 0rept 4__decstr __NS,__NFTFL_FPROT{__NS} equ MBAR_FTFL+$10 ; Program Flash Protection Register n (8b)PROT cffield FTFL_FPROT{__NS},0,8 ; Program Flash Region Protect__N set __N+1endmFTFL_FDPROT equ MBAR_FTFL+$14 ; Data Flash Protection Register (8b)DPROT cffield FTFL_FDPROT,0,8 ; Data Flash Region ProtectFTFL_FEPROT equ MBAR_FTFL+$15 ; EEPROM Protection Register (8b)EPROT cffield FTFL_FEPROT,0,8 ; EEPROM Region Protect;----------------------------------------------------------------------------; 12-bit Digital-to-Analog ConverterMBAR_DAC0 equ MBAR+$0500__N set 0rept 16__decstr __NS,__NDAC0_DAT{__NS}H equ MBAR_DAC0+(__N*2) ; DAC Data High Register n (8b)DATA1 cffield DAC0_DAT{__NS}H,0,4DAC0_DAT{__NS}L equ MBAR_DAC0+(__N*2)+1 ; DAC Data Low Register n (8b)DATA0 cffield DAC0_DAT{__NS}L,0,8__N set __N+1endmDAC0_SR equ MBAR_DAC0+$20 ; DAC Status Register (8b)DACBFWMF cfbit DAC0_SR,2 ; DAC Buffer Watermark FlagDACBFRPTF cfbit DAC0_SR,1 ; DAC Buffer Read Pointer Top Position FlagDACBFRPBF cfbit DAC0_SR,0 ; DAC Buffer Read Pointer Bottom Position FlagDAC0_C0 equ MBAR_DAC0+$21 ; DAC Control Register (8b)DACEN cfbit DAC0_C0,7 ; DAC EnableDACRFS cfbit DAC0_C0,6 ; DAC Reference SelectDACTRGSEL cfbit DAC0_C0,5 ; DAC Trigger SelectDACSWTRG cfbit DAC0_C0,4 ; DAC Software TriggerLPEN cfbit DAC0_C0,3 ; DAC Low Power ControlDACBWIEN cfbit DAC0_C0,2 ; DAC Buffer Watermark Interrupt EnableDACBTIEN cfbit DAC0_C0,1 ; DAC Buffer Read Pointer Top Flag Interrupt EnableDACBBIEN cfbit DAC0_C0,0 ; DAC Buffer Read Pointer Bottom Flag Interrupt EnableDAC0_C1 equ MBAR_DAC0+$22 ; DAC Control Register 1 (8b)DMAEN cfbit DAC0_C1,7 ; DMA Enable SelectDACBFWM cffield DAC0_C1,3,2 ; DAC Buffer Watermark SelectDACBFMD cffield DAC0_C1,1,2 ; DAC Buffer Work Mode SelectDACBFEN cfbit DAC0_C1,0 ; DAC Buffer EnableDAC0_C2 equ MBAR_DAC0+$23 ; DAC Control Register 2 (8b)DACBFRP cffield DAC0_C2,4,4 ; DAC Buffer Read PointerDACBFUP cffield DAC0_C2,0,4 ; DAC Buffer Upper Limit;----------------------------------------------------------------------------; High Speed Analog Comparator (includes mux control and 6-bit DAC control)MBAR_CMP0 equ MBAR+$0530CMP0_CR0 equ MBAR_CMP0+$30 ; CMP Control Register 0 (8b)FILTER_CNT cffield CMP0_CR0,4,3 ; Filter Sample CountHYSTCTR cffield CMP0_CR0,0,2 ; Comparator hard block hysteresis controlCMP0_CR1 equ MBAR_CMP0+$31 ; CMP Control Register 1 (8b)SE cfbit CMP0_CR1,7 ; Sample EnableWE cfbit CMP0_CR1,6 ; Windowing EnablePMODE cfbit CMP0_CR1,4 ; Power Mode SelectINV cfbit CMP0_CR1,3 ; Comparator INVERTCOS cfbit CMP0_CR1,2 ; Comparator Output SelectOPE cfbit CMP0_CR1,1 ; Comparator Output Pin EnableEN cfbit CMP0_CR1,0 ; Comparator Module EnableCMP0_FPR equ MBAR_CMP0+$32 ; CMP Filter Period Register (8b)FILT_PER cffield CMP0_FPR,0,8 ; Filter Sample PeriodCMP0_SCR equ MBAR_CMP0+$33 ; CMP Status and Control Register (8b)DMAEN cfbit CMP0_SCR,6 ; DMA Enable ControlSMELB cfbit CMP0_SCR,5 ; Stop Mode Edge/Level Interrupt ControlIER cfbit CMP0_SCR,4 ; Comparator Interrupt Enable RisingIEF cfbit CMP0_SCR,3 ; Comparator Interrupt Enable FallingCFR cfbit CMP0_SCR,2 ; Analog Comparator Flag RisingCFF cfbit CMP0_SCR,1 ; Analog Comparator Flag FallingCOUT cfbit CMP0_SCR,0 ; Analog Comparator OutputCMP0_DACCR equ MBAR_CMP0+$34 ; DAC Control Register (8b)DACEN cfbit CMP0_DACCR,7 ; DAC EnableVRSEL cfbit CMP0_DACCR,6 ; Supply Voltage Reference Source SelectVOSEL cffield CMP0_DACCR,0,6 ; DAC Output Voltage SelectCMP0_MUXCR equ MBAR_CMP0+$35 ; MUX Control Register (8b)PEN cfbit CMP0_MUXCR,7 ; PMUX EnableMEN cfbit CMP0_MUXCR,6 ; MMUX EnablePSEL cffield CMP0_MUXCR,3,3 ; Plus Input Mux ControlMSEL cffield CMP0_MUXCR,0,3 ; Minus Input Mux Control;----------------------------------------------------------------------------; Programmable Delay BlockMBAR_PDB0 equ MBAR+$0540PDB0_SC equ MBAR_PDB0+$00 ; Status and Control Register (32b)LDMOD cffield PDB0_SC,18,2 ; Load Mode SelectPDBEIE cfbit PDB0_SC,17 ; PDB Sequence Error Interrupt EnableSWTRIG cfbit PDB0_SC,16 ; Software TriggerDMAEN cfbit PDB0_SC,15 ; DMA EnablePRESCALER cffield PDB0_SC,12,3 ; Prescaler Divider SelectTRGSEL cffield PDB0_SC,8,4 ; Trigger Input Source SelectPDBEN cfbit PDB0_SC,7 ; PDB EnablePDBIF cfbit PDB0_SC,6 ; PDB Interrupt FlagPDBIE cfbit PDB0_SC,5 ; PDB Interrupt EnableMULT cffield PDB0_SC,2,2 ; Multiplication Factor Select for PrescalerCONT cfbit PDB0_SC,1 ; Continuous Mode EnableLDOK cfbit PDB0_SC,0 ; Load OKPDB0_MOD equ MBAR_PDB0+$04 ; Modulus Register (32b)MOD cffield PDB0_MOD,0,16 ; PDB ModulusPDB0_CNT equ MBAR_PDB0+$08 ; Counter Register (32b)CNT cffield PDB0_CNT,0,16 ; PDB CounterPDB0_IDLY equ MBAR_PDB0+$0C ; Interrupt Delay Register (32b)IDLY cffield PDB0_IDLY,0,16 ; PDB Interrupt DelayPDB0_CH0C1 equ MBAR_PDB0+$10 ; Channel n Control Register 1 (32b)BB cffield PDB0_CH0C1,16,8 ; PDB Channel Pre-Trigger Back-to-Back Operation EnableTOS cffield PDB0_CH0C1,8,8 ; PDB Channel Pre-Trigger Output SelectEN cffield PDB0_CH0C1,0,8 ; PDB Channel Pre-Trigger EnablePDB0_CH0S equ MBAR_PDB0+$14 ; Channel n Status Register (32b)CF cffield PDB0_CH0S,16,8 ; PDB Channel FlagsERR cffield PDB0_CH0S,0,8 ; PDB Channel Sequence Error FlagsPDB0_CH0DLY0 equ MBAR_PDB0+$18 ; Channel n Delay 0 Register (32b)DLY cffield PDB0_CH0DLY0,0,16 ; PDB Channel DelayPDB0_CH0DLY1 equ MBAR_PDB0+$1C ; Channel n Delay 1 Register (32b)DLY cffield PDB0_CH0DLY1,0,16 ; PDB Channel DelayPDB0_DACINTC0 equ MBAR_PDB0+$20 ; DAC Interval Trigger n Control Register (32b)EXT cfbit PDB0_DACINTC0,1 ; DAC External Trigger Input EnableTOE cfbit PDB0_DACINTC0,0 ; DAC Interval Trigger EnablePDB0_DACINT0 equ MBAR_PDB0+$24 ; DAC Interval n Register (32b)INT cffield PDB0_DACINT0,0,16 ; DAC IntervalPDB0_PO0EN equ MBAR_PDB0+$28 ; Pulse-Out n Enable Register (32b)POEN cffield PDB0_PO0EN,0,8 ; PDB Pulse-Out EnablePDB0_PO0DLY equ MBAR_PDB0+$2C ; Pulse-Out n Delay Register (32b)DLY1 cffield PDB0_PO0DLY,16,16 ; PDB Pulse-Out Delay 1DLY2 cffield PDB0_PO0DLY,0,16 ; PDB Pulse-Out Delay 2;----------------------------------------------------------------------------; Cyclic Redundancy Check GeneratorMBAR_CRC equ MBAR+$0570CRC_CRC equ MBAR_CRC+$00 ; CRC Data Register (32b)HU cffield CRC_CRC,24,8 ; CRC High Upper ByteHL cffield CRC_CRC,16,8 ; CRC High Lower ByteLU cffield CRC_CRC,8,8 ; CRC Low Upper ByteLL cffield CRC_CRC,0,8 ; CRC Low Lower ByteCRC_GPOLY equ MBAR_CRC+$04 ; CRC Polynomial Register (32b)HIGH cffield CRC_GPOLY,16,16 ; High polynominal half-wordLOW cffield CRC_GPOLY,0,16 ; Low polynominal half-wordCRC_CTRL equ MBAR_CRC+$08 ; CRC Control Register (16b)TOT cffield CRC_CTRL,14,2 ; Type of Transpose for WritesTOTR cffield CRC_CTRL,12,2 ; Type of Transpose for ReadFXOR cfbit CRC_CTRL,10 ; Complement Read of CRC data registerWAS cfbit CRC_CTRL,9 ; Write CRC data register as seedTCRC cfbit CRC_CTRL,8 ; Width of CRC protocol;----------------------------------------------------------------------------; Cryptographic Acceleration Unit; CAU Registers (CAx)CASR equ $0CAA equ $1CA0 equ $2CA1 equ $3CA2 equ $4CA3 equ $5CA4 equ $6CA5 equ $7CA6 equ $8CA7 equ $9CA8 equ $A; CAU CommandsCNOP equ $000LDR equ $010STR equ $020ADR equ $030RADR equ $040ADRA equ $050XOR equ $060ROTL equ $070MVRA equ $080MVAR equ $090AESS equ $0A0AESIS equ $0B0AESC equ $0C0AESIC equ $0D0AESR equ $0E0AESIR equ $0F0DESR equ $100DESK equ $110HASH equ $120SHS equ $130MDS equ $140SHS2 equ $150ILL equ $1F0; DESR FieldsIP equ $08 ; initial permutationFP equ $04 ; final permutationKSL1 equ $00 ; key schedule left 1 bitKSL2 equ $01 ; key schedule left 2 bitsKSR1 equ $02 ; key schedule right 1 bitKSR2 equ $03 ; key schedule right 2 bits; DESK FieldDC equ $01 ; decrypt key scheduleCP equ $02 ; check parity; HASH Functions CodesHFF equ $0 ; MD5 F() CA1&CA2 | ~CA1&CA3HFG equ $1 ; MD5 G() CA1&CA3 | CA2&~CA3HFH equ $2 ; MD5 H(), SHA Parity() CA1^CA2^CA3HFI equ $3 ; MD5 I() CA2^(CA1|~CA3)HFC equ $4 ; SHA Ch() CA1&CA2 ^ ~CA1&CA3HFM equ $5 ; SHA Maj() CA1&CA2 ^ CA1&CA3 ^ CA2&CA3HF2C equ $6 ; SHA-256 Ch() CA4&CA5 ^ ~CA4&CA6HF2M equ $7 ; SHA-256 Maj() CA0&CA1 ^ CA0&CA2 ^ CA1&CA2HF2S equ $8 ; SHA-256 Sigma 0 ROTR2(CA0)^ROTR13(CA0)^ROTR22(CA0)HF2T equ $9 ; SHA-256 Sigma 1 ROTR6(CA4)^ROTR11(CA4)^ROTR25(CA4)HF2U equ $A ; SHA-256 sigma 0 ROTR7(CA8)^ROTR18(CA8)^SHR3(CA8)HF2V equ $B ; SHA-256 sigma 1 ROTR17(CA8)^ROTR19(CA8)^SHR10(CA8);----------------------------------------------------------------------------; Successive Approximation Analog-to-Digital Converter (16-bit)MBAR_ADC0 equ MBAR+$0600ADC0_SC1A equ MBAR_ADC0+$00 ; ADC Status and Control Registers 1 (32b)COCO cfbit ADC0_SC1A,7 ; Conversion Complete FlagAIEN cfbit ADC0_SC1A,6 ; Interrupt EnableDIFF cfbit ADC0_SC1A,4 ; Differential Mode EnableADCH cffield ADC0_SC1A,0,5 ; Input channel selectADC0_SC1B equ MBAR_ADC0+$04 ; ADC Status and Control Registers 1 (32b)COCO cfbit ADC0_SC1B,7 ; Conversion Complete FlagAIEN cfbit ADC0_SC1B,6 ; Interrupt EnableDIFF cfbit ADC0_SC1B,4 ; Differential Mode EnableADCH cffield ADC0_SC1B,0,5 ; Input channel selectADC0_CFG1 equ MBAR_ADC0+$08 ; ADC Configuration Register 1 (32b)ADLPC cfbit ADC0_CFG1,7 ; Low-Power ConfigurationADIV cffield ADC0_CFG1,5,2 ; Clock Divide SelectADLSMP cfbit ADC0_CFG1,4 ; Sample time configurationMODE cffield ADC0_CFG1,2,2 ; Conversion mode selectionADICLK cffield ADC0_CFG1,0,2 ; Input Clock SelectADC0_CFG2 equ MBAR_ADC0+$0C ; ADC Configuration Register 2 (32b)ADACKEN cfbit ADC0_CFG2,3 ; Asynchronous Clock Output EnableADHSC cfbit ADC0_CFG2,2 ; High-Speed ConfigurationADLSTS cffield ADC0_CFG2,0,2 ; Long Sample Time SelectADC0_RA equ MBAR_ADC0+$10 ; ADC Data Result Register (32b)ADC0_RB equ MBAR_ADC0+$14 ; ADC Data Result Register (32b)ADC0_CV1 equ MBAR_ADC0+$18 ; Compare Value Registers (32b)ADC0_CV2 equ MBAR_ADC0+$1C ; Compare Value Registers (32b)ADC0_SC2 equ MBAR_ADC0+$20 ; Status and Control Register 2 (32b)ADACT cfbit ADC0_SC2,7 ; Conversion ActiveADTRG cfbit ADC0_SC2,6 ; Conversion Trigger SelectACFE cfbit ADC0_SC2,5 ; Compare Function EnableACFGT cfbit ADC0_SC2,4 ; Compare Function Greater Than EnableACREN cfbit ADC0_SC2,3 ; Compare Function Range EnableDMAEN cfbit ADC0_SC2,2 ; DMA EnableREFSEL cffield ADC0_SC2,0,2 ; Voltage Reference SelectionADC0_SC3 equ MBAR_ADC0+$24 ; Status and Control Register 3 (32b)CAL cfbit ADC0_SC3,7 ; CalibrationCALF cfbit ADC0_SC3,6 ; Calibration Failed FlagADCO cfbit ADC0_SC3,3 ; Continuous Conversion EnableAVGE cfbit ADC0_SC3,2 ; Hardware Average EnableAVGS cffield ADC0_SC3,0,2 ; Hardware Average SelectADC0_OFS equ MBAR_ADC0+$28 ; ADC Offset Correction Register (32b)OFS cffield ADC0_OFS,0,16 ; Offset Error Correction ValueADC0_PG equ MBAR_ADC0+$2C ; ADC Plus-Side Gain Register (32b)PG cffield ADC0_PG,0,16 ; Plus-Side GainADC0_MG equ MBAR_ADC0+$30 ; ADC Minus-Side Gain Register (32b)MG cffield ADC0_MG,0,16 ; Minus-Side GainADC0_CLPD equ MBAR_ADC0+$34 ; ADC Plus-Side General Calibration Value Register (32b)CLPD cffield ADC0_CLPD,0,6 ; Calibration ValueADC0_CLPS equ MBAR_ADC0+$38 ; ADC Plus-Side General Calibration Value Register (32b)CLPS cffield ADC0_CLPS,0,6 ; Calibration ValueADC0_CLP4 equ MBAR_ADC0+$3C ; ADC Plus-Side General Calibration Value Register (32b)CLP4 cffield ADC0_CLP4,0,10 ; Calibration ValueADC0_CLP3 equ MBAR_ADC0+$40 ; ADC Plus-Side General Calibration Value Register (32b)CLP3 cffield ADC0_CLP3,0,9 ; Calibration ValueADC0_CLP2 equ MBAR_ADC0+$44 ; ADC Plus-Side General Calibration Value Register (32b)CLP2 cffield ADC0_CLP2,0,8 ; Calibration ValueADC0_CLP1 equ MBAR_ADC0+$48 ; ADC Plus-Side General Calibration Value Register (32b)CLP1 cffield ADC0_CLP1,0,7 ; Calibration ValueADC0_CLP0 equ MBAR_ADC0+$4C ; ADC Plus-Side General Calibration Value Register (32b)CLP0 cffield ADC0_CLP0,0,6 ; Calibration ValueADC0_CLMD equ MBAR_ADC0+$54 ; ADC Minus-Side General Calibration Value Register (32b)CLMD cffield ADC0_CLMD,0,6 ; Calibration ValueADC0_CLMS equ MBAR_ADC0+$58 ; ADC Minus-Side General Calibration Value Register (32b)CLMS cffield ADC0_CLMS,0,6 ; Calibration ValueADC0_CLM4 equ MBAR_ADC0+$5C ; ADC Minus-Side General Calibration Value Register (32b)CLM4 cffield ADC0_CLM4,0,10 ; Calibration ValueADC0_CLM3 equ MBAR_ADC0+$60 ; ADC Minus-Side General Calibration Value Register (32b)CLM3 cffield ADC0_CLM3,0,9 ; Calibration ValueADC0_CLM2 equ MBAR_ADC0+$64 ; ADC Minus-Side General Calibration Value Register (32b)CLM2 cffield ADC0_CLM2,0,8 ; Calibration ValueADC0_CLM1 equ MBAR_ADC0+$68 ; ADC Minus-Side General Calibration Value Register (32b)CLM1 cffield ADC0_CLM1,0,7 ; Calibration ValueADC0_CLM0 equ MBAR_ADC0+$6C ; ADC Minus-Side General Calibration Value Register (32b)CLM0 cffield ADC0_CLM0,0,6 ; Calibration Value;----------------------------------------------------------------------------; Voltage ReferenceMBAR_VREF equ MBAR+$0670VREF_TRM equ MBAR_VREF+$00 ; VREF Trim Register (8b)TRIM cffield VREF_TRM,0,6 ; Trim bitsVREF_SC equ MBAR_VREF+$01 ; VREF Status and Control Register (8b)VREFEN cfbit VREF_SC,7 ; Internal Voltage Reference enableREGEN cfbit VREF_SC,6 ; Regulator enableICOMPEN cfbit VREF_SC,5 ; Second order curvature compensation enableVREFST cfbit VREF_SC,2 ; Internal Voltage Reference stableMODE_LV cffield VREF_SC,0,2 ; Buffer Mode selection;----------------------------------------------------------------------------; Port I/O Control Module__defpioctl macro ID,Base,FilterPCTL{ID}_PUE equ Base+$00 ; Port Pulling Enable Register (8b)__enumbits PCTL{ID}_PUE,PTPUE,8 ; Port internal pulling enable bitsPCTL{ID}_PUS equ Base+$01 ; Port Pullup/Pulldown Select Register (8b)__enumbits PCTL{ID}_PUS,PTPUS,8 ; Port pullup/pulldown select bitsPCTL{ID}_DS equ Base+$02 ; Port Drive Strength Enable Register (8b)__enumbits PCTL{ID}_DS,PTDS,8 ; Port output drive strength control bitsPCTL{ID}_SRE equ Base+$03 ; Port Slew Rate Enable Register (8b)__enumbits PCTL{ID}_SRE,PTSRE,8 ; Port output slow rate enable bitsPCTL{ID}_PFE equ Base+$04 ; Port Passive Filter Enable Register (8b)__enumbits PCTL{ID}_PFE,PTPFE,8, ; Port passive input filter enable bitsPCTL{ID}_IC equ Base+$05 ; Port Interrupt Control Register (8b)PTDMAEN cfbit PCTL{ID}_IC,7 ; DMA enablePTIE cfbit PCTL{ID}_IC,1 ; Interrupt enablePTMOD cfbit PCTL{ID}_IC,0 ; Direction mode for pin interruptPCTL{ID}_IPE equ Base+$06 ; Port Interrupt Pin Enable Register (8b)__enumbits PCTL{ID}_IPE,PTIPE,8 ; Interrupt pin enablesPCTL{ID}_IF equ Base+$07 ; Port Interrupt Flag Register (8b)__enumbits PCTL{ID}_IF,PTIF,8 ; Interrupt flagsPCTL{ID}_IES equ Base+$08 ; Interrupt Edge Select Register (8b)__enumbits PCTL{ID}_IES,PTEDG,8 ; Edge selects of pin interruptif FilterPCTL{ID}_DFE equ Base+$09 ; Port Digital Filter Enable Register__enumbits PCTL{ID}_DFE,PTDFE,8 ; Digital filter enablesPCTL{ID}_DFC equ Base+$0a ; Port Digital Filter Control RegisterPTCLKS cfbit PCTL{ID}_DFC,7 ; Clock select bitPTFF cffield PCTL{ID}_DFC,0,5 ; Filter factor bitsendifendm__defpioctl "A",MBAR+$1200,0__defpioctl "B",MBAR+$1210,1__defpioctl "C",MBAR+$1220,1__defpioctl "D",MBAR+$1230,0__defpioctl "E",MBAR+$1240,0__defpioctl "F",MBAR+$1250,0;----------------------------------------------------------------------------; Touch Sensing InputMBAR_TSI0 equ MBAR+$1400TSI0_GENCS equ MBAR_TSI0+$000 ; General Control and Status Register (32b)LPCLKS cfbit TSI0_GENCS,28 ; Low Power Mode Clock Source SelectionLPSCNITV cffield TSI0_GENCS,24,4 ; TSI Low Power Mode Scan IntervalNSCN cffield TSI0_GENCS,19,5 ; Number of Consecutive Scans per ElectrodePS cffield TSI0_GENCS,16,3 ; Electrode oscillator prescalerEOSF cfbit TSI0_GENCS,15 ; End of scan flagOUTRGF cfbit TSI0_GENCS,14 ; Out of Range FlagEXTERF cfbit TSI0_GENCS,13 ; External electrode error occurredOVRF cfbit TSI0_GENCS,12 ; Overrun error flagSCNIP cfbit TSI0_GENCS,9 ; Scan-in-progress statusSWTS cfbit TSI0_GENCS,8 ; Software trigger startTSIEN cfbit TSI0_GENCS,7 ; TSI module enableTSIIE cfbit TSI0_GENCS,6 ; TSI interrupt enableERIE cfbit TSI0_GENCS,5 ; TSI error interrupt EnableESOR cfbit TSI0_GENCS,4 ; End-of-scan or out-of-range interrupt selectSTM cfbit TSI0_GENCS,1 ; Scan trigger modeSTPE cfbit TSI0_GENCS,0 ; TSI stop enable while in low-power modesTSI0_SCANC equ MBAR_TSI0+$004 ; SCAN control register (32b)REFCHRG cffield TSI0_SCANC,27,5 ; Reference oscillator charge current selectCAPTRM cffield TSI0_SCANC,24,3 ; Internal capacitance trim valueEXTCHRG cffield TSI0_SCANC,19,5 ; External oscillator charge current selectDELVOL cffield TSI0_SCANC,16,3 ; Delta voltage select applied to analog oscillatorsSMOD cffield TSI0_SCANC,8,8 ; Scan moduloAMCLKDIV cfbit TSI0_SCANC,5 ; Active mode clock dividerAMCLKS cffield TSI0_SCANC,3,2 ; Active mode clock sourceAMPSC cffield TSI0_SCANC,0,3 ; Active mode prescalerTSI0_PEN equ MBAR_TSI0+$008 ; Pin enable register (32b)LPSP cffield TSI0_PEN,16,4 ; Low-power scan pin__enumbits TSI0_PEN,PEN,16 ; TSI pin n enableTSI0_STATUS equ MBAR_TSI0+$00C ; Status Register (32b)__enumbits_o TSI0_STATUS,ERROF,16,16,-16; TouchSensing Error Flag n__enumbits TSI0_STATUS,ORNGF,16 ; Touch Sensing Electrode Out-of-Range Flag n__N set 0rept 8__decstr __NS,__N*2+1TSI0_CNTR{__NS} equ MBAR_TSI0+$100+(__N*4) ; Counter Register (32b)CTN cffield TSI0_CNTR{__NS},16,16 ; TouchSensing channel n counter valueCTN1 cffield TSI0_CNTR{__NS},0,16 ; TouchSensing channel n-1 counter value__N set __N+1endm__N set 0rept 16__decstr __NS,__NTSI0_THRESHLD{__NS} equ MBAR_TSI0+$120+(__N*4) ; Channel n threshold register (32b)LTHH cffield TSI0_THRESHLD{__NS},16,16 ; Low threshold valueHTHH cffield TSI0_THRESHLD{__NS},0,16 ; High threshold value__N set __N+1endm;----------------------------------------------------------------------------; Random Number Generator BlockMBAR_RNGB equ MBAR+$18c0RNG_VER equ MBAR_RNGB+$00 ; RNGB Version ID Register (32b)TYPE cffield RNG_VER,28,4 ; Random number generator typeMAJOR cffield RNG_VER,8,8 ; Major version numberMINOR cffield RNG_VER,0,8 ; Minor version numberRNG_CMD equ MBAR_RNGB+$04 ; RNGB Command Register (32b)SR cfbit RNG_CMD,6 ; Software resetCE cfbit RNG_CMD,5 ; Clear errorCI cfbit RNG_CMD,4 ; Clear interruptGS cfbit RNG_CMD,1 ; Generate seedST cfbit RNG_CMD,0 ; Self testRNG_CR equ MBAR_RNGB+$08 ; RNGB Control Register (32b)MASKERR cfbit RNG_CR,6 ; Mask error interruptMASKDONE cfbit RNG_CR,5 ; Mask done interruptAR cfbit RNG_CR,4 ; Auto-reseedFUFMOD cffield RNG_CR,0,2 ; FIFO underflow response modeRNG_SR equ MBAR_RNGB+$0C ; RNGB Status Register (32b)STATPF cffield RNG_SR,24,8 ; Statistics test pass failST_PF cffield RNG_SR,21,3 ; Self Test Pass FailERR cfbit RNG_SR,16 ; ErrorFIFO_SIZE cffield RNG_SR,12,4 ; FIFO sizeFIFO_LVL cffield RNG_SR,8,4 ; FIFO levelNSDN cfbit RNG_SR,6 ; New seed doneSDN cfbit RNG_SR,5 ; Seed doneSTDN cfbit RNG_SR,4 ; Self test doneRS cfbit RNG_SR,3 ; Reseed neededSLP cfbit RNG_SR,2 ; SleepBUSY cfbit RNG_SR,1 ; BusyRNG_ESR equ MBAR_RNGB+$10 ; RNGB Error Status Register (32b)FUFE cfbit RNG_ESR,4 ; FIFO underflow errorSATE cfbit RNG_ESR,3 ; Statistical test errorSTE cfbit RNG_ESR,2 ; Self test errorOSCE cfbit RNG_ESR,1 ; Oscillator errorLFE cfbit RNG_ESR,0 ; Linear feedback shift register (LFSR) errorRNG_OUT equ MBAR_RNGB+$14 ; RNGB Output FIFO (32b)RANDOUT cffield RNG_OUT,0,32 ; Random Output;----------------------------------------------------------------------------; Direct Memory Access ControllerMBAR_DMA equ MBAR+$6400DMA_REQC equ MBAR_DMA+$000 ; DMA Request Control Register (32b)CFSM0 cfbit DMA_REQC,31 ; Clear state machine control 0DMAC0 cffield DMA_REQC,24,4 ; DMA channel 0 sourceCFSM1 cfbit DMA_REQC,23 ; Clear state machine control 1DMAC1 cffield DMA_REQC,16,4 ; DMA channel 1 sourceCFSM2 cfbit DMA_REQC,15 ; Clear state machine control 2DMAC2 cffield DMA_REQC,8,4 ; DMA channel 2 sourceCFSM3 cfbit DMA_REQC,7 ; Clear state machine control 3DMAC3 cffield DMA_REQC,0,4 ; DMA channel 3 source__defdma macro NUM,OffsetDMA_SAR{NUM} equ MBAR_DMA+Offset+$00 ; Source Address Register (32b)DMA_DAR{NUM} equ MBAR_DMA+Offset+$04 ; Destination Address Register (32b)DMA_DSR_BCR{NUM} equ MBAR_DMA+Offset+$08 ; DMA Status Register / Byte Count Register (32b)CE cfbit DMA_DSR_BCR{NUM},30 ; Configuration errorBES cfbit DMA_DSR_BCR{NUM},29 ; Bus error on sourceBED cfbit DMA_DSR_BCR{NUM},28 ; Bus error on destinationREQ cfbit DMA_DSR_BCR{NUM},26 ; RequestBSY cfbit DMA_DSR_BCR{NUM},25 ; BusyDONE cfbit DMA_DSR_BCR{NUM},24 ; Transactions doneBCR cffield DMA_DSR_BCR{NUM},0,24 ; number of bytes yet to be transferred for a given blockDMA_DCR{NUM} equ MBAR_DMA+Offset+$0c ; DMA Control Register (32b)EINT cfbit DMA_DCR{NUM},31 ; Enable interrupt on completion of transferERQ cfbit DMA_DCR{NUM},30 ; Enable peripheral requestCS cfbit DMA_DCR{NUM},29 ; Cycle stealAA cfbit DMA_DCR{NUM},28 ; Auto-alignSINC cfbit DMA_DCR{NUM},22 ; Source incrementSSIZE cffield DMA_DCR{NUM},20,2 ; Source sizeDINC cfbit DMA_DCR{NUM},19 ; Destination incrementDSIZE cffield DMA_DCR{NUM},17,2 ; Destination sizeSTART cfbit DMA_DCR{NUM},16 ; Start transferSMOD cffield DMA_DCR{NUM},12,4 ; Source address moduloDMOD cffield DMA_DCR{NUM},8,4 ; Destination address moduloD_REQ cfbit DMA_DCR{NUM},7 ; Disable requestLINKCC cffield DMA_DCR{NUM},4,2 ; Link channel controlLCH1 cffield DMA_DCR{NUM},2,2 ; Link channel 1LCH2 cffield DMA_DCR{NUM},0,2 ; Link channel 2endm__defdma "0",$00__defdma "1",$10__defdma "2",$20__defdma "3",$30;----------------------------------------------------------------------------; External Memory InterfaceMBAR_MB equ MBAR+$6800__defcs macro NUM,BaseFB_CSAR{NUM} equ Base+0 ; Chip Select n Address Register (32b)BA cffield FB_CSAR{NUM},16,16 ; Base Address bits 16..31FB_CSMR{NUM} equ Base+4 ; Chip Select n Mask Register (32b)BAM cffield FB_CSMR{NUM},16,16 ; Base Address MaskWP cfbit FB_CSMR{NUM},8 ; Write ProtectV cfbit FB_CSMR{NUM},0 ; ValidFB_CSCR{NUM} equ Base+8 ; Chip Select n Control Register (32b)ASET cffield FB_CSCR{NUM},20,2 ; Address SetupRDAH cffield FB_CSCR{NUM},18,2 ; Read Address Hold or DeselectWRAH cffield FB_CSCR{NUM},16,2 ; Write Address Hold or DeselectWS cffield FB_CSCR{NUM},10,6 ; Wait statesMUX cfbit FB_CSCR{NUM},9 ; Multiplexed ModeAA cfbit FB_CSCR{NUM},8 ; Auto-Acknowledge EnablePS cffield FB_CSCR{NUM},6,2 ; Port sizeendm;----------------------------------------------------------------------------; V1 ColdFire Interrupt ControllerMBAR_INTC equ MBAR+$7fc0INTC_IMRH equ MBAR_INTC+$08 ; Interrupt Mask Register High (32b)IMR43 cfbit INTC_IMRH,11 ; Interrupt mask register 43IMR42 cfbit INTC_IMRH,10 ; Interrupt mask register 42IMR41 cfbit INTC_IMRH,9 ; Interrupt mask register 41IMR40 cfbit INTC_IMRH,8 ; Interrupt mask register 40IMR39 cfbit INTC_IMRH,7 ; Interrupt mask register 39IMR38 cfbit INTC_IMRH,6 ; Interrupt mask register 38IMR37 cfbit INTC_IMRH,5 ; Interrupt mask register 37IMR36 cfbit INTC_IMRH,4 ; Interrupt mask register 36IMR35 cfbit INTC_IMRH,3 ; Interrupt mask register 35IMR34 cfbit INTC_IMRH,2 ; Interrupt mask register 34IMR33 cfbit INTC_IMRH,1 ; Interrupt mask register 33IMR32 cfbit INTC_IMRH,0 ; Interrupt mask register 32INTC_IMRL equ MBAR_INTC+$0C ; Interrupt Mask Register Low (32b)IMR31 cfbit INTC_IMRL,31 ; Interrupt mask register 31IMR30 cfbit INTC_IMRL,30 ; Interrupt mask register 30IMR29 cfbit INTC_IMRL,29 ; Interrupt mask register 29IMR28 cfbit INTC_IMRL,28 ; Interrupt mask register 28IMR27 cfbit INTC_IMRL,27 ; Interrupt mask register 27IMR26 cfbit INTC_IMRL,26 ; Interrupt mask register 26IMR25 cfbit INTC_IMRL,25 ; Interrupt mask register 25IMR24 cfbit INTC_IMRL,24 ; Interrupt mask register 24IMR23 cfbit INTC_IMRL,23 ; Interrupt mask register 23IMR22 cfbit INTC_IMRL,22 ; Interrupt mask register 22IMR21 cfbit INTC_IMRL,21 ; Interrupt mask register 21IMR20 cfbit INTC_IMRL,20 ; Interrupt mask register 20IMR19 cfbit INTC_IMRL,19 ; Interrupt mask register 19IMR18 cfbit INTC_IMRL,18 ; Interrupt mask register 18IMR17 cfbit INTC_IMRL,17 ; Interrupt mask register 17IMR16 cfbit INTC_IMRL,16 ; Interrupt mask register 16IMR15 cfbit INTC_IMRL,15 ; Interrupt mask register 15IMR14 cfbit INTC_IMRL,14 ; Interrupt mask register 14IMR13 cfbit INTC_IMRL,13 ; Interrupt mask register 13IMR12 cfbit INTC_IMRL,12 ; Interrupt mask register 12IMR11 cfbit INTC_IMRL,11 ; Interrupt mask register 11IMR10 cfbit INTC_IMRL,10 ; Interrupt mask register 10IMR9 cfbit INTC_IMRL,9 ; Interrupt mask register 9IMR8 cfbit INTC_IMRL,8 ; Interrupt mask register 8IMR7 cfbit INTC_IMRL,7 ; Interrupt mask register 7IMR6 cfbit INTC_IMRL,6 ; Interrupt mask register 6IMR5 cfbit INTC_IMRL,5 ; Interrupt mask register 5IMR4 cfbit INTC_IMRL,4 ; Interrupt mask register 4IMR3 cfbit INTC_IMRL,3 ; Interrupt mask register 3IMR2 cfbit INTC_IMRL,2 ; Interrupt mask register 2IMR1 cfbit INTC_IMRL,1 ; Interrupt mask register 1IMR0 cfbit INTC_IMRL,0 ; Interrupt mask register 0INTC_FRC equ MBAR_INTC+$10 ; Force Interrupt Register (8b)LVL1 cfbit INTC_FRC,6 ; Force level 1 interruptLVL2 cfbit INTC_FRC,5 ; Force level 2 interruptLVL3 cfbit INTC_FRC,4 ; Force level 3 interruptLVL4 cfbit INTC_FRC,3 ; Force level 4 interruptLVL5 cfbit INTC_FRC,2 ; Force level 5 interruptLVL6 cfbit INTC_FRC,1 ; Force level 6 interruptLVL7 cfbit INTC_FRC,0 ; Force level 7 interruptINTC_PL6P7 equ MBAR_INTC+$18 ; INTC Programmable Level 6 Priority Registers (8b)REQN cffield INTC_PL6P7,0,6 ; Request numberINTC_PL6P6 equ MBAR_INTC+$19 ; INTC Programmable Level 6 Priority Registers (8b)REQN cffield INTC_PL6P6,0,6 ; Request numberINTC_WCR equ MBAR_INTC+$1B ; INTC Wakeup Control Register (8b)ENB cfbit INTC_WCR,7 ; Enable wakeup signalMASK cffield INTC_WCR,0,3 ; Interrupt mask levelINTC_SIMR equ MBAR_INTC+$1C ; Set Interrupt Mask Register (8b)SALL cfbit INTC_SIMR,6 ; Set allSIMR cffield INTC_SIMR,0,6 ; Set IMRINTC_CIMR equ MBAR_INTC+$1D ; Clear Interrupt Mask Register (8b)CALL cfbit INTC_CIMR,6 ; Clear allCIMR cffield INTC_CIMR,0,6 ; Clear IMRINTC_SFRC equ MBAR_INTC+$1E ; INTC Set Interrupt Force Register (8b)SET cffield INTC_SFRC,0,6 ; For data values within the 56-62 range, the corresponding bit in the INTC_FRC register is setINTC_CFRC equ MBAR_INTC+$1F ; INTC Clear Interrupt Force Register (8b)CLR cffield INTC_CFRC,0,6 ; For data values within the 56-62 range, the corresponding bit in the INTC_FRC register is clearedINTC_SWIACK equ MBAR_INTC+$20 ; INTC Software IACK Register (8b)VECN cffield INTC_SWIACK,0,7 ; Vector number__N set 1rept 7__decstr __NS,__NINTC_LVL{__NS}IACK equ MBAR_INTC+$20+(__N*4) ; INTC Level-n IACK Registers (8b)VECN cffield INTC_LVL{__NS}IACK,0,7 ; Vector number__N set __N+1endm;----------------------------------------------------------------------------restoreendif ; __mcf51qminc