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ifndef __mcf5307inc ; avoid multiple inclusion__mcf5307inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File MCF5307.INC *;* *;* Contains SFR and Bit Definitions for ColdFire MCF5307 *;* *;****************************************************************************ifndef MBARMBAR equ $fc000000warning "MBAR not set - assume default value $fc000000"endif;----------------------------------------------------------------------------; System Integration ModuleRSR equ MBAR+$0 ; Reset Status Register (8b)HRST cfbit RSR,7 ; Hardware or System ResetSWTR cfbit RSR,5 ; Software Watchdog Timer ResetSYPCR equ MBAR+$1 ; System Protection Control Register (8b)SWE cfbit SYPCR,7 ; Software Watchdog Timer enableSWRI cfbit SYPCR,6 ; Software Watchdog Reset/Interrupt SelectSWP cfbit SYPCR,5 ; Software Watchdog PrescalerSWT cffield SYPCR,3,2 ; Software Watchdog Timing DelaySWTA cfbit SYPCR,2 ; Software Watchdog Transfer Acknowledge EnableSWTAVAL cfbit SYPCR,1 ; Software Watchdog Transfer Acknowledge ValidSWIVR equ MBAR+$2 ; Software Watchdog Interrupt Vector Register (8b)SWIV cffield SWIVR,0,7SWSR equ MBAR+$3 ; Software Watchdog Service Register (8b)PAR equ MBAR+$4 ; Pin Assignment Register (32b)IRQPAR equ MBAR+$6 ; Interrupt Port Assignment Register (8b)IRQPAR2 cfbit IRQPAR,7IRQPAR1 cfbit IRQPAR,6IRQPAR0 cfbit IRQPAR,5PLLCR equ MBAR+$8 ; PLL Control (8b)ENBSTOP cfbit PLLCR,7 ; Enable CPU STOP InstructionPLLIPL cffield PLLCR,4,3 ; PLL Interrupt Priority Level to Wake Up from CPU STOPMPARK equ MBAR+$c ; Default Bus Master Park Register (8b)PARK cffield MPARK,6,2 ; ParkIARBCTRL cfbit MPARK,5 ; Internal Bus Arbitration ControlEARBCTRL cfbit MPARK,4 ; External Bus Arbitration ControlSHOWDATA cfbit MPARK,3 ; Enable Internal Register Data Bus to be Driven on External BusBCR24BIT cfbit MPARK,0 ; BCR and Address Mapping for DMA;----------------------------------------------------------------------------; I2CMBAR_I2C equ MBAR+$280include "52xxi2c.inc";----------------------------------------------------------------------------; Interrupt ControllerMBAR_IC equ MBAR+$40__defipmr macro {INTLABEL},Base__LABEL__ equ BaseDMA3 cfbit __LABEL__,17 ; DMA3DMA2 cfbit __LABEL__,16 ; DMA2DMA1 cfbit __LABEL__,15 ; DMA1DMA0 cfbit __LABEL__,14 ; DMA0UART1 cfbit __LABEL__,13 ; UART1UART0 cfbit __LABEL__,12 ; UART0I2C cfbit __LABEL__,11 ; I2CTIMER1 cfbit __LABEL__,10 ; Timer1TIMER0 cfbit __LABEL__,9 ; Timer0SWT cfbit __LABEL__,8 ; Software Watchdog TimerEINT7 cfbit __LABEL__,7 ; External Interrupt 7EINT6 cfbit __LABEL__,6 ; External Interrupt 6EINT5 cfbit __LABEL__,5 ; External Interrupt 5EINT4 cfbit __LABEL__,4 ; External Interrupt 4EINT3 cfbit __LABEL__,3 ; External Interrupt 3EINT2 cfbit __LABEL__,2 ; External Interrupt 2EINT1 cfbit __LABEL__,1 ; External Interrupt 1endmIPR __defipmr MBAR_IC+0 ; Interrupt Pending Register (32b)IMR __defipmr MBAR_IC+4 ; Interrupt Mask Register (32b)AVR equ MBAR_IC+11 ; Autovector Register (8b)AVEC cffield AVR,1,7 ; Autovector ControlBLK cfbit AVR,0 ; Block Address Strobe__deficr macro Num,BaseICR{Num} equ BaseAVEC cfbit ICR{Num},7 ; Autovector EnableIL cffield ICR{Num},2,3 ; Interrupt LevelIP cffield ICR{Num},0,2 ; Interrupt Priorityendm__deficr "0",MBAR_IC+12 ; Software Watchdog Timer__deficr "1",MBAR_IC+13 ; Timer0__deficr "2",MBAR_IC+14 ; Timer1__deficr "3",MBAR_IC+15 ; I2C__deficr "4",MBAR_IC+16 ; UART0__deficr "5",MBAR_IC+17 ; UART1__deficr "6",MBAR_IC+18 ; DMA0__deficr "7",MBAR_IC+19 ; DMA1__deficr "8",MBAR_IC+20 ; DMA2__deficr "9",MBAR_IC+21 ; DMA3;----------------------------------------------------------------------------; Chip Select ModuleMBAR_CS equ MBAR+$80__N set 0rept 8__decstr __NS,__NCSAR{__NS} equ MBAR_CS+(__N*12)+0 ; Chip-Select Address Register (16b)BA cffield CSAR{__NS},0,16 ; Base Address (upper 16 bits)CSMR{__NS} equ MBAR_CS+(__N*12)+4 ; Chip-Select Mask Register (32b)BAM cffield CSMR{__NS},16,16 ; Base Address MaskWP cfbit CSMR{__NS},8 ; Write ProtectAM cfbit CSMR{__NS},6 ; Alternate masterCI cfbit CSMR{__NS},5 ; CPU space and interrupt acknowledge cycle maskSC cfbit CSMR{__NS},4 ; Supervisor Code Address Space MaskSD cfbit CSMR{__NS},3 ; Supervisor Data Address Space MaskUC cfbit CSMR{__NS},2 ; User Code Address Space MaskUD cfbit CSMR{__NS},1 ; User Data Address Space MaskV cfbit CSMR{__NS},0 ; ValidCSCR{__NS} equ MBAR_CS+(__N*12)+8 ; Chip-Select Control Register (16b)WS cffield CSCR{__NS},10,4 ; Wait StatesAA cfbit CSCR{__NS},8 ; Auto-Acknowledge EnablePS cffield CSCR{__NS},6,2 ; Port SizeBEM cfbit CSCR{__NS},5 ; Bus Master EmableBSTR cfbit CSCR{__NS},4 ; Burst-Read EnableBSTW cfbit CSCR{__NS},3 ; Burst-Write Enable__N set __N+1endm;----------------------------------------------------------------------------; DRAM ControllerMBAR_DRAM equ MBAR+$100DCR equ MBAR_DRAM+0 ; DRAM Control Register (16b)SO cfbit DCR,15 ; Synchronous OperationNAM cfbit DCR,13 ; No Address MultiplexingRRA cffield DCR,11,2 ; Refresh /RAS AssertedRRP cffield DCR,9,2 ; Refresh /RAS PrechargeRC cffield DCR,0,9 ; Refresh Count__defsdcs macro N,AddrDACR{N} equ Addr+0 ; Address and Control Register (32b)BA cffield DACR{N},18,14 ; Base AddressRE cfbit DACR{N},15 ; Refresh EnableCAS cffield DACR{N},12,2 ; /CAS TimingRP cfbit DACR{N},10,2 ; /RAS Precharge TimingRNCN cffield DACR{N},9 ; /RAS-Negate-to-/CAS-NegateRCD cfbit DACR{N},8 ; /RAS-to-/CAS DelayEDO cfbit DACR{N},6 ; Extended Data OutPS cffield DACR{N},4,2 ; Port SizePM cffield DACR{N},2,2 ; Page ModeDMR{N} equ Addr+4 ; Mask Register (32b)BAM cffield DMR{N},18,14 ; Base Address MaskWP cfbit DMR{N},8 ; Write ProtectCI cfbit DMR{N},6 ; CPU Space/Interrupt AcknowledgeAM cfbit DMR{N},5 ; Alternate MasterSC cfbit DMR{N},4 ; Supervisor CodeSD cfbit DMR{N},3 ; Supervisor DataUC cfbit DMR{N},2 ; User CodeUD cfbit DMR{N},1 ; User DataV cfbit DMR{N},0 ; Validendm__defsdcs "0",MBAR_DRAM+8__defsdcs "1",MBAR_DRAM+16;----------------------------------------------------------------------------; DMA ControllerMBAR_DMA equ MBAR+$300__N set 0rept 4__decstr __NS,__NSAR{__NS} equ MBAR_DMA+(__N*64)+0 ; Source Address Register (32b)DAR{__NS} equ MBAR_DMA+(__N*64)+4 ; Destination Address Register (32b)DCR{__NS} equ MBAR_DMA+(__N*64)+8 ; Control Register (32b)INT cfbit DCR{__NS},31 ; Interrupt on Completion of TransferEEXT cfbit DCR{__NS},30 ; Enable External RequestCS cfbit DCR{__NS},29 ; Cycle StealAA cfbit DCR{__NS},28 ; Auto-AlignBWC cffield DCR{__NS},25,3 ; Bandwidth ControlSAA cfbit DCR{__NS},24 ; Single-Address AccessS_RW cfbit DCR{__NS},23 ; Single-Address Access Read/Write ValueSINC cfbit DCR{__NS},22 ; Source IncrementSSIZE cffield DCR{__NS},20,2 ; Source SizeDINC cfbit DCR{__NS},19 ; Destination IncrementDSIZE cffield DCR{__NS},17,2 ; Destination SizeSTART cfbit DCR{__NS},16 ; Start TransferAT cfbit DCR{__NS},15 ; DMA Acknowledge TypeBCR{__NS} equ MBAR_DMA+(__N*64)+12 ; Byte Count Register (32b)DSR{__NS} equ MBAR_DMA+(__N*64)+16 ; Status Register (8b)CE cfbit DSR{__NS},6 ; Configuration ErrorBES cfbit DSR{__NS},5 ; Bus Error on SourceBED cfbit DSR{__NS},4 ; Bus Error on DestinationREQ cfbit DSR{__NS},2 ; RequestBSY cfbit DSR{__NS},1 ; BusyDONE cfbit DSR{__NS},0 ; Transactions DoneDIVR{__NS} equ MBAR_DMA+(__N*64)+20 ; Interrupt Vector Register (8b)__N set __N+1endm;----------------------------------------------------------------------------; Timerinclude "52xxtmr.inc"__deftimer "0",MBAR+$140__deftimer "1",MBAR+$180;----------------------------------------------------------------------------; UARTsinclude "53xxuart.inc"__defuart "0",MBAR+$140__defuart "1",MBAR+$200;----------------------------------------------------------------------------; Parallel PortPADDR equ MBAR+$244 ; Port A Data Direction Register (16b)PADAT equ MBAR+$248 ; Port A Data Register (16b)restore ; re-enable listingendif ; __mcf5307inc