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ifndef _artim16inc ; avoid multiple inclusion_artim16inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File ARTIM16.INC *;* *;* contains SFR and Bit Definitions for ST62xx 16 Bit AR Timer *;* *;****************************************************************************SCR1 sfr 0e8h ; Status Control Register 1PSC bfield SCR1,6,2 ; Clock PrescalerRELOAD bit 5,SCR1 ; Reload EnabledRUNRES bit 4,SCR1 ; Run/ResetOVFIEN bit 3,SCR1 ; Overflow Interrupt EnableOVFFLG bit 2,SCR1 ; Overflow OccuredOVFMD bit 1,SCR1 ; Overflow Output ModeSCR2 sfr 0e1h ; Status Control Register 2CP1ERR bit 6,SCR2 ; CP1 Error FlagCP2ERR bit 5,SCR2 ; CP2 Error FlagCP1IEN bit 4,SCR2 ; CP1 Interrupt EnableCP1FLG bit 3,SCR2 ; CP1 Interrupt FlagCP1POL bit 2,SCR2 ; CP1 Edge Polarity SelectRLDSEL bfield SCR2,0,2 ; Reload Source SelectSCR3 sfr 0e2h ; Status Control Register 3CP2POL bit 7,SCR3 ; CP2 Edge Polarity SelectCP2IEN bit 6,SCR3 ; CP2 Interrupt EnableCP2FLG bit 5,SCR3 ; CP2 Interrupt FlagCMPIEN bit 4,SCR3 ; Compare Interrupt EnableCMFLG bit 3,SCR3 ; Compare FlagZEROIEN bit 2,SCR3 ; Compare to Zero Int EnableZEROFLG bit 1,SCR3 ; Compare to Zero FlagPWMMD bit 0,SCR3 ; PWM Output Mode ControlSCR4 sfr 0e3h ; Status Control Register 4OVFPOL bit 3,SCR4 ; Overflow Output PolarityOVFEN bit 2,SCR4 ; Overflow Output EnablePMPOL bit 1,SCR4 ; PWM Output PolarityPWMEN bit 0,SCR4 ; PWM Output EnableRLCPH sfr 0e9h ; Reload/Capture Register High ByteRLCPL sfr 0eah ; Reload/Capture Register Low ByteCPH sfr 0ebh ; Capture Register High ByteCPL sfr 0ech ; Capture Register Low ByteCMPH sfr 0edh ; Compare Register High ByteCMPL sfr 0eeh ; Compare Register Low ByteMASKH sfr 0efh ; Mask Register High ByteMASKL sfr 0e0h ; Mask Register Low Byterestoreendif ; _artim16inc