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ifndef __reg6228inc ; avoid multiple inclusion__reg6228inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File REG6228.INC *;* *;* contains SFR and Bit Definitions for ST6228 *;* *;* Source: ST62T28C/E28C Data Sheet, Rev. 2.9, July 2001 *;* *;****************************************************************************;----------------------------------------------------------------------------; Memory AddressesRAMSTART sfr 0000h ; Start Address Internal RAM; area 00h..3fh maps to two banks; area 40h..7fh is ROM read windowRAMEND sfr 00bfh ; End Address Internal RAMROMSTART label 0080h ; Start Address Internal ROMROMEND label 1fffh ; End " " ROM;----------------------------------------------------------------------------; Interrupt VectorsADC_vect label 0ff0h ; A/D End Of Conversion, shared with...TIMER_vect label 0ff0h ; Timer Underflow, shared with...UART_vect label 0ff0h ; UART Tx/Rx InterruptARTIMER_vect label 0ff2h ; AR Timer Overflow/CapturePORTD_vect label 0ff4h ; Ext. Interrupt Port D, shared with...PORTB_vect label 0ff4h ; Ext. Interrupt Port BSPI_vect label 0ff6h ; SPI Interrupt, shared with...PORTA_vect label 0ff6h ; Ext. Interrupt Port APORTC_vect label 0ffch ; Ext. Interrupt Port C, shared with...NMI_vect label 0ffch ; Non Maskable InterruptRESET_vect label 0ffeh ; RESET;----------------------------------------------------------------------------; GPIOinclude "gpio.inc"__defgpio "A",0c0h__defgpio "B",0c1h__defgpio "C",0c2h__defgpio "D",0c3h;----------------------------------------------------------------------------; CPUinclude "ior.inc"DRBR sfr 0cbh ; Data RAM Bank RegisterDRBR4 bit 4,DRBR ; Map RAM Page 2DRBR3 bit 3,DRBR ; Map RAM Page 1IPR sfr 0dah ; Interrupt Polarity RegisterPortD bit 3,IPR ; Port D Interrupt PolarityPortC bit 2,IPR ; Port C Interrupt PolarityPortA bit 1,IPR ; Port A Interrupt PolarityPortB bit 0,IPR ; Port B Interrupt Polarity;----------------------------------------------------------------------------; Watchdoginclude "wdg.inc"DWDR sfr WDGR ; alternate name in older data sheets;----------------------------------------------------------------------------; Analog/Digital Converterinclude "adc.inc"OSCOFF bit 2,ADCR ; Main Oscillator OffCLSEL bit 3,ADCR ; Clock Selection;----------------------------------------------------------------------------; Timer 1include "timer.inc"__deftimer 0d2h,""TOUT bit 5,TSCR ; Timer Output ControlDOUT bit 4,TSCR ; Data Output;----------------------------------------------------------------------------; Auto Reload Timerinclude "artimer.inc"__defartimer 0e0h;----------------------------------------------------------------------------; UARTinclude "uart.inc";----------------------------------------------------------------------------; SPIinclude "spi.inc"restoreendif ; __reg6228inc