Blame | Last modification | View Log | Download | RSS feed
ifndef __reg6253inc ; avoid multiple inclusion__reg6253inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File REG6253.INC *;* *;* contains SFR and Bit Definitions for ST6253/6260/6263 *;* *;* Source: ST62T53C/T60C/T63C, ST62E60C Data Sheet, Rev. 2.8, July 2001 *;* *;****************************************************************************;----------------------------------------------------------------------------; Memory AddressesRAMSTART sfr 000h ; Start Address Internal RAM; area 00h..3fh maps to one RAM bank; area 40h..7fh is ROM read windowRAMEND sfr 0bfh ; End Address Internal RAMswitch MOMCPUNAMEcase "ST6253"case "ST6260"EESTART sfr 0000h ; Start Address EEPROM (two banks shared with RAM)EEEND sfr 003fh ; End " "case "ST6263"EESTART sfr 0000h ; Start Address EEPROM (one bank shared with RAM)EEEND sfr 003fh ; End " "elsecasefatal "Huh?"endcasesegment codeROMSTART label 0880h ; Start Address Internal ROMROMEND label 0fffh ; End " " ROM;----------------------------------------------------------------------------; Interrupt VectorsADC_vect label 0ff0h ; A/D End Of Conversion, shared with...TIMER_vect label 0ff0h ; Timer UnderflowARTIMER_vect label 0ff2h ; AR Timer Overflow/ComparePORTC_vect label 0ff4h ; Ext. Interrupt Port C, shared with...SPI_vect label 0ff4h ; SPI InterruptPORTA_vect label 0ff6h ; Ext. Interrupt Port A, shared with...PORTB_vect label 0ff6h ; Ext. Interrupt Port BNMI_vect label 0ffch ; Non Maskable InterruptRESET_vect label 0ffeh ; RESET;----------------------------------------------------------------------------; GPIOinclude "gpio.inc"__defgpio "A",0c0h__defgpio "B",0c1h__defgpio "C",0c2h;----------------------------------------------------------------------------; CPUinclude "ior.inc"DRBR sfr 0e8h ; Data RAM Bank RegisterDRBR4 bit 4,DRBR ; Map RAM Page 2ifdef EESTARTif MOMCPUNAME="ST6260"DRBR1 bit 4,DRBR ; Map EEPROM Page 1endifDRBR0 bit 0,DRBR ; Map EEPROM Page 0endififdef EESTARTEECTL sfr 0eah ; EEPROM Control RegisterE2OFF bit 6,EECTL ; Stand-by Enable BitE2PAR1 bit 3,EECTL ; Parallel Start BitE2PAR2 bit 2,EECTL ; Parallel Mode EnE2BUSY bit 1,EECTL ; EEPROM Busy BitE2ENA bit 0,EECTL ; EEPROM Enable BitendifOSCCTL sfr 0dch ; Oscillator ControlRS bfield OSCCTL,0,2 ; Division Ratio;----------------------------------------------------------------------------; Watchdoginclude "wdg.inc"DWDR sfr WDGR ; alternate name in older data sheets;----------------------------------------------------------------------------; Analog/Digital Converterinclude "adc.inc"OSCOFF bit 2,ADCR ; Disable Main Oscillator;----------------------------------------------------------------------------; Timerinclude "timer.inc"__deftimer 0d2h,"";----------------------------------------------------------------------------; AR Timerinclude "artimer.inc"__defartimer 0d0h;----------------------------------------------------------------------------; SPIinclude "spi2.inc"restoreendif ; __reg6253inc