Blame | Last modification | View Log | Download | RSS feed
ifndef stddef56inc ; avoid multiple inclusionstddef56inc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File STDDEF56.INC *;* *;* Contains SFR Definitions for the DSP56000 *;* *;****************************************************************************if (MOMCPU<>352256)fatal "wrong target selected: only 56000 allowed"endifif MOMPASS=1message "DSP56000 SFR Definitions (C) 1993 Alfred Arnold"endif;---------------------------------------------------------------------------pbc xsfr $ffe0 ; Port B Bus Control Registerpbddr xsfr $ffe2 ; Port B Data Direction Registerpbd xsfr $ffe4 ; Port B Data Registerpcc xsfr $ffe1 ; Port C Control Registerpcddr xsfr $ffe3 ; Port C Data Direction Registerpcd xsfr $ffe5 ; Port C Data Registerhcr xsfr $ffe8 ; Host Control Registerhsr xsfr $ffe9 ; Host Status Registerhtx xsfr $ffeb ; Host Transmit Registerhrx xsfr htx ; Host Receive Registercra xsfr $ffec ; SSI Control Register Acrb xsfr $ffed ; SSI Control Register Btsr xsfr $ffee ; SSI Status/Time Slot Registertx xsfr $ffef ; SCI Transmit Registerrx xsfr tx ; SCI Receive Registerscr xsfr $fff0 ; SCI Interface Control Registerssr xsfr $fff1 ; SCI Interface Status Registersccr xsfr $fff2 ; SCI Control Registerstxa xsfr $fff3 ; SCI Transmit Data Address Registersrx xsfr $fff4 ; SCI Receive Register Base Addresstx xsfr srx ; SCI Transmit Register Base Addressrx_lo xsfr srx ; SCI Receive Register in Bits 0..7stx_lo xsfr stx ; SCI Transmit Register in Bits 0..7srx_mid xsfr srx+1 ; SCI Receive Register in Bits 8..15stx_mid xsfr stx+1 ; SCI Transmit Register in Bits 8..15srx_hi xsfr srx+2 ; SCI Receive Register in Bits 16..23stx_hi xsfr stx+2 ; SCI Transmit Register in Bits 16..23bcr xsfr $fffe ; Bus Control Registeripr xsfr $ffff ; Interrupt Priority Register;---------------------------------------------------------------------------restore ; allow listing againendif ; stddef56inc