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ifndef __stm8lcompinc ; avoid multiple inclusion__stm8lcompinc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File COMP.INC *;* *;* contains SFR and Bit Definitions for STM8L Comparator(s) *;* *;****************************************************************************__defcomp macro BaseCOMP_CSR1 label Base+$00 ; Comparator control and status register 1COMP_IE1 bit COMP_CSR1,5 ; Comparator 1 interrupt enableCOMP_EF1 bit COMP_CSR1,4 ; Comparator 1 event flagCOMP_CMP1OUT bit COMP_CSR1,3 ; Comparator 1 outputCOMP_STE bit COMP_CSR1,2 ; Schmitt trigger enableCOMP_CMP1 bfield COMP_CSR1,0,2 ; Comparator 1 configurationCOMP_CSR2 label Base+$01 ; Comparator control and status register 2COMP_IE2 bit COMP_CSR2,5 ; Comparator 2 Interrupt EnableCOMP_EF2 bit COMP_CSR2,4 ; Comparator 2 event flagCOMP_CMP2OUT bit COMP_CSR2,3 ; Comparator 2 outputCOMP_SPEED bit COMP_CSR2,2 ; Comparator 2 speed modeCOMP_CMP2 bfield COMP_CSR2,0,2 ; Comparator 2 configurationCOMP_CSR3 label Base+$02 ; Comparator control and status register 3COMP_OUTSEL bfield COMP_CSR3,6,2 ; Comparator 2 output selectionCOMP_INSEL bfield COMP_CSR3,3,3 ; Comparator 2 inverting input selectionCOMP_VREFEN bit COMP_CSR3,2 ; Internal reference voltage VREFINT enableCOMP_WNDWE bit COMP_CSR3,1 ; Window mode enableCOMP_VREFOUTEN bit COMP_CSR3,0 ; VREFINT output enableCOMP_CSR4 label Base+$03 ; Comparator control and status register 4COMP_NINVTRIG bfield COMP_CSR4,3,3 ; COMP2 non inverting inputCOMP_INVTRIG bfield COMP_CSR4,0,3 ; COMP2 inverting inputCOMP_CSR5 label Base+$04 ; Comparator control and status register 5COMP_DACTRIG bfield COMP_CSR5,3,3 ; DAC outputsCOMP_VREFTRIG bfield COMP_CSR5,0,3 ; VREFINT outputsendmrestoreendif ; __stm8lcompinc