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ifndef __stm8lrtcinc ; avoid multiple inclusion__stm8lrtcinc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File RTC.INC *;* *;* contains SFR and Bit Definitions for STM8L RTC *;* *;****************************************************************************__defrtc macro BaseRTC_TR1 label Base+$00 ; RTC Time register 1RTC_ST bfield RTC_TR1,4,3 ; Second tens in BCD formatRTC_SU bfield RTC_TR1,0,4 ; Second units in BCD formatRTC_TR2 label Base+$01 ; RTC Time register 2RTC_MNT bfield RTC_TR2,4,3 ; Minute tens in BCD formatRTC_MNU bfield RTC_TR2,0,4 ; Minute units in BCD formatRTC_TR3 label Base+$02 ; RTC Time register 3RTC_PM bit RTC_TR3,7 ; AM/PM notationRTC_HT bfield RTC_TR3,4,2 ; Hour tens in BCD formatRTC_HU bfield RTC_TR3,0,4 ; Hour units in BCD formatRTC_DR1 label Base+$04 ; RTC Date register 1RTC_DT bfield RTC_DR1,4,2 ; Date tens in BCD formatRTC_DU bfield RTC_DR1,0,4 ; Date units in BCD formatRTC_DR2 label Base+$05 ; RTC Date register 2RTC_WDU bfield RTC_DR2,5,3 ; Week day unitsRTC_MT bit RTC_DR2,4 ; Month tens in BCD formatRTC_MU bfield RTC_DR2,0,4 ; Month units in BCD formatRTC_DR3 label Base+$06 ; RTC Date register 3RTC_YT bfield RTC_DR3,4,4 ; Year tens in BCD formatRTC_YU bfield RTC_DR3,0,4 ; Year units in BCD formatRTC_CR1 label Base+$08 ; RTC Control register 1RTC_FMT bit RTC_CR1,6 ; Hour formatRTC_RATIO bit RTC_CR1,5 ; System clock (SYSCLK) versus RTCCLK ratioRTC_BYPSHAD bit RTC_CR1,4 ; Bypass the shadow registersRTC_WUCKSEL bfield RTC_CR1,0,3 ; Wakeup clock selectionRTC_CR2 label Base+$09 ; RTC Control register 2RTC_WUTIE bit RTC_CR2,6 ; Wakeup timer interrupt enableRTC_ALRAIE bit RTC_CR2,4 ; Alarm A interrupt enableRTC_WUTE bit RTC_CR2,2 ; Wakeup timer enableRTC_ALRAE bit RTC_CR2,0 ; Alarm A enableRTC_CR3 label Base+$0a ; RTC Control register 3RTC_COE bit RTC_CR3,7 ; Calibration output enableRTC_OSEL bfield RTC_CR3,5 ; Output selectionRTC_POL bit RTC_CR3,4 ; Output polarityRTC_COSEL bit RTC_CR3,3 ; Calibration output selectionRTC_BCK bit RTC_CR3,2 ; BackupRTC_SUB1H bit RTC_CR3,1 ; Subtract 1 hour (winter time change)RTC_ADD1H bit RTC_CR3,0 ; Add 1 hour (summer time change)RTC_ISR1 label Base+$0c ; RTC Initialization and status register 1RTC_INIT bit RTC_ISR1,7 ; Initialization modeRTC_INITF bit RTC_ISR1,6 ; Initialization flagRTC_RSF bit RTC_ISR1,5 ; Registers synchronization flagRTC_INITS bit RTC_ISR1,4 ; Initialization status flagRTC_SHPF bit RTC_ISR1,3 ; Shift operation pendingRTC_WUTWF bit RTC_ISR1,2 ; Wakeup timer write flagRTC_RECALPF bit RTC_ISR1,1 ; Recalibration pending FlagRTC_ALRAWF bit RTC_ISR1,0 ; Alarm A write flagRTC_ISR2 label Base+$0d ; RTC Initialization and Status register 2RTC_TAMP3F bit RTC_ISR2,7 ; TAMPER3 detection flagRTC_TAMP2F bit RTC_ISR2,6 ; TAMPER2 detection flagRTC_TAMP1F bit RTC_ISR2,5 ; TAMPER1 detection flagRTC_WUTF bit RTC_ISR2,2 ; Periodic wakeup flagRTC_ALRAF bit RTC_ISR2,0 ; Alarm A FlagRTC_SPRERH label Base+$10 ; RTC Synchronous prescaler register highRTC_SPRERL label Base+$11 ; RTC Synchronous prescaler register lowRTC_APRER label Base+$12 ; RTC Asynchronous prescaler registerRTC_WUTRH label Base+$14 ; RTC Wakeup timer register highRTC_WUTRL label Base+$15 ; RTC Wakeup timer register lowRTC_SSRL label Base+$17 ; RTC Subsecond register lowRTC_SSRH label Base+$18 ; RTC Subsecond register highRTC_WPR label Base+$19 ; RTC Write protection registerRTC_SHIFTRH label Base+$1a ; RTC Shift register highRTC_ADD1S bit RTC_SHIFTRH,7 ; Add one secondRTC_SHIFTRL label Base+$1b ; RTC Shift register lowRTC_ALRMAR1 label Base+$1c ; RTC Alarm A register 1RTC_MSK1 bit RTC_ALRMAR1,7 ; Alarm A Seconds maskRTC_AL_ST bfield RTC_ALRMAR1,4,3 ; Second tens in BCD formatRTC_AL_SU bfield RTC_ALRMAR1,0,4 ; Second units in BCD formatRTC_ALRMAR2 label Base+$1d ; RTC Alarm A register 2RTC_MSK2 bit RTC_ALRMAR2,7 ; Alarm A minutes maskRTC_AL_MNT bfield RTC_ALRMAR2,4,3 ; Minute tens in BCD formatRTC_AL_MNU bfield RTC_ALRMAR2,0,4 ; Minute units in BCD formatRTC_ALRMAR3 label Base+$1e ; RTC Alarm A register 3RTC_MSK3 bit RTC_ALRMAR3,7 ; Alarm A hours maskRTC_AL_PM bit RTC_ALRMAR3,6 ; AM/PM notationRTC_AL_HT bfield RTC_ALRMAR3,4,2 ; Hour tens in BCD formatRTC_AL_HU bfield RTC_ALRMAR3,0,4 ; Hour units in BCD formatRTC_ALRMAR4 label Base+$1f ; RTC Alarm A register 4RTC_MSK4 bit RTC_ALRMAR4,7 ; Alarm A Date maskRTC_WDSEL bit RTC_ALRMAR4,6 ; Week day selectionRTC_AL1_DT bfield RTC_ALRMAR4,4,2 ; Date tens in BCD formatRTC_AL1_DU bfield RTC_ALRMAR4,0,4 ; Date units or Day in BCD formatRTC_ALRMASSRH label Base+$24 ; RTC Alarm A subsecond register highRTC_ALRMASSRL label Base+$25 ; RTC Alarm A subsecond register lowRTC_ALRMASSMSKR label Base+$26 ; RTC Alarm A masking registerRTC_CALRH label Base+$2a ; RTC Calibration register highRTC_CALP bit RTC_CALRH,7 ; Increase of RTC frequency by 488.5 ppmRTC_CALW8 bit RTC_CALRH,6 ; Use an 8-second calibration cycle periodRTC_CALW16 bit RTC_CALRH,5 ; Use a16-second calibration cycle periodRTC_CALRL label Base+$2b ; RTC Calibration register lowRTC_TCR1 label Base+$2c ; RTC Tamper control register 1RTC_TAMP3TRG bit RTC_TCR1,6 ; Active level for tamper input 3RTC_TAMP3E bit RTC_TCR1,5 ; Tamper detection enable for tamper input 3RTC_TAMP2TRG bit RTC_TCR1,4 ; Active level for tamper input 2RTC_TAMP2E bit RTC_TCR1,3 ; Tamper detection enable for tamper input 2RTC_TAMP1TRG bit RTC_TCR1,2 ; Active level for tamper 1RTC_TAMP1E bit RTC_TCR1,1 ; Tamper detection enable for tamper input 1RTC_TAMPIE bit RTC_TCR1,0 ; Tamper interrupt enableRTC_TCR2 label Base+$2d ; RTC Tamper control register 2RTC_TTAMPPUDIS bit RTC_TCR2,7 ; TAMPER pull-up disableRTC_TTAMPPRCH bfield RTC_TCR2,5,2 ; Tamper precharge durationRTC_TTAMPFLT bfield RTC_TCR2,3,2 ; Tamper filter countRTC_TTAMPFREQ bfield RTC_TCR2,0,2 ; Tamper sampling frequencyCSSLSE_CSR label Base+$50 ; CSS on LSE control and status registerSWITCHF bit CSSLSE_CSR,4 ; RTC clock switch flagCSSF bit CSSLSE_CSR,3 ; CSS on LSE flagCSSIE bit CSSLSE_CSR,2 ; Clock security system on LSE interrupt enableSWITCHEN bit CSSLSE_CSR,1 ; RTC clock switch to LSI in case of LSE failure enableLSE_CSSEN bit CSSLSE_CSR,0 ; Clock security system on LSE enableendmrestoreendif ; __stm8lrtcinc