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ifndef __stm8sspiinc ; avoid multiple inclusion__stm8sspiinc equ 1savelisting off ; no listing over this file;****************************************************************************;* *;* AS 1.42 - File SPI.INC *;* *;* contains SFR and Bit Definitions for STM8S SPI *;* *;****************************************************************************__defspi macro BaseSPI_CR1 label Base+$00 ; SPI control register 1SPI_LSBFIRST bit SPI_CR1,7 ; Frame formatSPI_SPE bit SPI_CR1,6 ; SPI enableSPI_BR bfield SPI_CR1,3,3 ; Baud rate controlSPI_MSTR bit SPI_CR1,2 ; Master selectionSPI_CPOL bit SPI_CR1,1 ; Clock polaritySPI_CPHA bit SPI_CR1,0 ; Clock phaseSPI_CR2 label Base+$01 ; SPI control register 2SPI_BDM bit SPI_CR2,7 ; Bidirectional data mode enableSPI_BDOE bit SPI_CR2,6 ; Input/Output enable in bidirectional modeSPI_CRCEN bit SPI_CR2,5 ; Hardware CRC calculation enableSPI_CRCNEXT bit SPI_CR2,4 ; Transmit CRC nextSPI_RXONLY bit SPI_CR2,2 ; Receive onlySPI_SSM bit SPI_CR2,1 ; Software slave managementSPI_SSI bit SPI_CR2,0 ; Internal slave selectSPI_ICR label Base+$02 ; SPI interrupt control registerSPI_TXIE bit SPI_ICR,7 ; Tx buffer empty interrupt enableSPI_RXIE bit SPI_ICR,6 ; RX buffer not empty interrupt enableSPI_ERRIE bit SPI_ICR,5 ; Error interrupt enableSPI_WKIE bit SPI_ICR,4 ; Wakeup interrupt enableSPI_SR label Base+$03 ; SPI status registerSPI_BSY bit SPI_SR,7 ; Busy flagSPI_OVR bit SPI_SR,6 ; Overrun flagSPI_MODF bit SPI_SR,5 ; Mode faultSPI_CRCERR bit SPI_SR,4 ; CRC error flagSPI_WKUP bit SPI_SR,3 ; Wakeup flagSPI_TXE bit SPI_SR,1 ; Transmit buffer emptySPI_RXNE bit SPI_SR,0 ; Receive buffer not emptySPI_DR label Base+$04 ; SPI data registerSPI_CRCPR label Base+$05 ; SPI CRC polynomial registerSPI_RXCRCR label Base+$06 ; SPI Rx CRC registerSPI_TXCRCR label Base+$07 ; SPI Tx CRC registerendmrestoreendif ; __stm8sspiinc