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Subversion Repositories
pentevo
?pathlinks? – Rev 896
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896
2020-11-14 20:24:33
lvd
/
pentevo: changing repo structure
722
2017-01-02 00:30:28
lvd
/
pentevo: nmi seems to be fixed now, also new .rbf and zxevo_fw have been built
721
2017-01-01 21:26:07
lvd
/fpga/current/sim_top/
pentevo: nmitest by DimkaM loaded and executes (no actual NMI)
720
2017-01-01 20:13:52
lvd
/fpga/current/sim_top/
pentevo: M48K without 'force'
684
2015-01-13 17:53:16
lvd
/
updated srcs for ULA emulation
576
2012-10-07 21:46:12
lvd
/fpga/current/
added breakpoint functionality (not tested, not compiled in avr firmware
543
2012-01-15 23:09:23
lvd
/
fpga/current: merged all features to current (avr sdcard access, updated NMI behavior, font read, some bugfixes), built new zxevo_fw.bin
511
2011-12-27 12:49:28
lvd
/fpga/current/sim_top/
changed simulation evnironment to support windows-based old modelsim, added signals to wave
510
2011-12-26 00:26:58
lvd
/fpga/current/
changed dram init in model; added waves to wave.do
469
2011-07-18 13:22:03
lvd
/fpga/current/
fpga/current: added 16bit buffer for read data
467
2011-07-14 23:08:27
lvd
/fpga/current/
merged z14 with trunk
425
2011-06-05 17:12:18
lvd
/fpga/current/
atm_nmi merging with current
280
2010-11-10 10:05:08
lvd
/fpga/current/
fpga/current: merged important changes from atm_mem2
200
2010-04-30 01:29:13
lvd
/fpga/current/
merged atm_mem to current
41
2009-12-11 00:31:20
lvd
/fpga/current/
continuing...
40
2009-12-08 00:12:49
lvd
/fpga/current/
starting redesign from two clocks (zports.v) to single clock (fclk) and zpos-zneg strobes (zclock.v). May be broken now, not tested in hardware
38
2009-12-06 01:53:17
lvd
/
Probably bugfix for NMOS bug; changed Makefile in avr/ to automatically take top.rbf from fpga/current
34
2009-12-05 12:25:39
lvd
/fpga/current/
tb somehow works, added timing info (oscillospoce screenshots) to z80/clocking
33
2009-12-04 00:39:35
lvd
/fpga/current/sim_top/
fixed bugs with Pullup1 going to vhld model
31
2009-12-03 21:38:49
lvd
/fpga/current/sim_top/
T80 does not work in simulation
29
2009-12-03 00:09:33
lvd
/fpga/current/sim_top/
complete testbench. does not work.