| 80 |
2017-10-31 16:00:04 |
lvd |
/branches/newclk/cpld/ |
zxiznet: newclk: changing design |
|
| 79 |
2017-10-31 15:20:04 |
lvd |
/branches/newclk/ |
zxiznet: making branch for new clocking/filtering system |
|
| 72 |
2017-09-19 13:30:36 |
lvd |
/trunk/cpld/rtl/ |
trunk: added clocked filter, patched testbench to pass tests with that filter |
|
| 70 |
2017-09-18 00:15:06 |
dimkam |
/trunk/cpld/ |
patch |
|
| 60 |
2013-10-03 10:12:41 |
lvd |
/trunk/cpld/ |
zxiznet: dir structure |
|
| 59 |
2013-10-03 10:09:34 |
lvd |
/trunk/cpld/ |
zxiznet: trying to fix glitches... |
|
| 48 |
2013-04-04 00:17:48 |
lvd |
/trunk/ |
zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built |
|
| 32 |
2012-11-11 22:20:16 |
lvd |
/trunk/ |
added port access to w5300 (HDL code, testbench, specs all updated) |
|
| 25 |
2012-11-03 23:41:28 |
lvd |
/trunk/ |
added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs |
|
| 23 |
2012-10-31 11:25:00 |
lvd |
/trunk/cpld/rtl/ |
updated verilog code according to new specs |
|
| 13 |
2012-10-13 19:38:42 |
lvd |
/trunk/cpld/ |
initial verilog code and quartus project (not tested\!) |
|