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Rev Age Author Path Log message Diff
67 2014-10-26 19:18:34 lvd /branches/clkfix/cpld/ clkfix: removing sl811_rst_n pin  
66 2014-10-26 19:05:30 lvd /branches/clkfix/ Spawning new branch "clkfix" to try to fix glitches by adding extra clock to FPGA  
60 2013-10-03 10:12:41 lvd /trunk/cpld/ zxiznet: dir structure  
59 2013-10-03 10:09:34 lvd /trunk/cpld/ zxiznet: trying to fix glitches...  
48 2013-04-04 00:17:48 lvd /trunk/ zxiznet: fixed reset behavior of ms bit: now it's reset only on zx reset, not on sl811 reset. doc fixed, new .pof built  
32 2012-11-11 22:20:16 lvd /trunk/ added port access to w5300 (HDL code, testbench, specs all updated)  
25 2012-11-03 23:41:28 lvd /trunk/ added USB master/slave switching circuits, changed HDL to buffer databus, removed BRDY read from specs  
23 2012-10-31 11:25:00 lvd /trunk/cpld/rtl/ updated verilog code according to new specs  
13 2012-10-13 19:38:42 lvd /trunk/cpld/ initial verilog code and quartus project (not tested\!)