| 66 |
2011-01-17 02:12:30 |
lvd |
/cpld/cpld5_buf/ |
cpld: fix by CHRV for no glitches |
|
| 60 |
2010-11-23 12:13:09 |
lvd |
/ |
rebuilt both cpld5 and fpgaF with Q72, updated a little NGS_prm |
|
| 58 |
2010-09-25 12:15:49 |
lvd |
/ |
cpld5_buf: recompiled with slow slew rate; added ramtests (fast and slow, slow for many freqs, fast for 24 only) |
|
| 49 |
2010-07-26 08:49:05 |
lvd |
/cpld/cpld5_buf/ |
updated pinout of CPLD for current .sch |
|
| 40 |
2010-05-15 13:07:59 |
chrv |
/cpld/cpld5_buf/ |
pin assigment (equal sch) |
|
| 30 |
2010-04-19 01:05:31 |
lvd |
/cpld/cpld5_buf/ |
testbench for cpld_buf finished and works with rtl, todo: run testbench on gate-level |
|
| 25 |
2010-04-09 23:26:34 |
lvd |
/cpld/cpld5_buf/ |
writing testbench for cpld_buf in progress |
|
| 22 |
2010-04-04 12:38:56 |
lvd |
/cpld/cpld5_buf/ |
testing of cpld_buf begins |
|
| 20 |
2010-03-21 20:51:29 |
lvd |
/ |
revC schematics updated, cpld5_buf updated for rev.C board: no checking, no pinmapping yet |
|
| 17 |
2010-03-18 01:18:08 |
lvd |
/ |
start of big changes in cpld5_buf and revC schematics \(probably\) |
|