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Rev	Age	Author	Path	Log message	Diff	Changes
34	2010-04-21 23:23:36	lvd	/cpld/cpld5_buf/	next iteration...		/cpld/cpld5_buf/GS_cpld.v /cpld/cpld5_buf/sim/tb.v /cpld/cpld5_buf/sim/wave.do
28	2010-04-15 01:04:37	lvd	/cpld/cpld5_buf/	testbench update in progress...		/cpld/cpld5_buf/GS_cpld.v /cpld/cpld5_buf/sim/tb.v
25	2010-04-09 23:26:34	lvd	/cpld/cpld5_buf/	writing testbench for cpld_buf in progress		/cpld/cpld5_buf/sim/GS_3032.txt /cpld/cpld5_buf/GS_cpld.pof /cpld/cpld5_buf/GS_cpld.qsf /cpld/cpld5_buf/GS_cpld.v /cpld/cpld5_buf/sim/tb.v /cpld/cpld5_buf/sim/wave.do /cpld/cpld5_buf/test1.cvwf
22	2010-04-04 12:38:56	lvd	/cpld/cpld5_buf/	testing of cpld_buf begins		/cpld/cpld5_buf/test1.cvwf /cpld/cpld5_buf/GS_cpld.pof /cpld/cpld5_buf/GS_cpld.qsf /cpld/cpld5_buf/GS_cpld.v
20	2010-03-21 20:51:29	lvd	/	revC schematics updated, cpld5_buf updated for rev.C board: no checking, no pinmapping yet		/cpld/cpld5_buf/GS_cpld.pof /cpld/cpld5_buf/GS_cpld.v /pcad/revC/NeoGS.sch /pcad/revC/none.txt
18	2010-03-18 13:04:41	lvd	/	Some suggestions		/cpld/cpld5_buf/GS_cpld.v /pcad/revC/NeoGS.sch /pcad/revC/none.txt
17	2010-03-18 01:18:08	lvd	/	start of big changes in cpld5_buf and revC schematics \(probably\)		/cpld/cpld5_buf/GS_cpld.pof /cpld/cpld5_buf/GS_cpld.qpf /cpld/cpld5_buf/GS_cpld.qsf /cpld/cpld5_buf/GS_cpld.v /pcad/revC/74_74LCX245.pdf /pcad/revC/none.txt /cpld/cpld5_buf/GS_3032.fit.summary /cpld/cpld5_buf/GS_3032.map.summary /cpld/cpld5_buf/GS_3032.qpf /cpld/cpld5_buf/GS_3032.qsf /cpld/cpld5_buf/GS_3032.tan.summary /cpld/cpld5_buf/GS_3032.v /pcad/revC/NeoGS.sch /pcad/revC/todo.txt
12	2009-12-20 21:11:25	lvd	/cpld/cpld5_buf/	added cpld variant for buffering Z80 busses to 3v memory		/cpld/cpld5_buf /cpld/cpld5_buf/GS_3032.fit.summary /cpld/cpld5_buf/GS_3032.map.summary /cpld/cpld5_buf/GS_3032.qpf /cpld/cpld5_buf/GS_3032.qsf /cpld/cpld5_buf/GS_3032.tan.summary /cpld/cpld5_buf/GS_3032.v /cpld/cpld5_buf/clocker.bdf