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(root)/fpga/ramtest_revC_slow/rnd_vec_gen/rnd_vec_gen.v @ 58 – Rev 0

Rev 0 – 2010-09-25 12:15:49
Author: lvd
Log message:
cpld5_buf: recompiled with slow slew rate; added ramtests (fast and slow, slow for many freqs, fast for 24 only)

Path	Blame	Diff	Log
/cpld/cpld5_buf/GS_cpld.pof
/cpld/cpld5_buf/GS_cpld.qsf
/cpld/cpld5_buf/sim/gate/GS_cpld.vo
/cpld/cpld5_buf/sim/gate/GS_cpld_v.sdo
/fpga/ramtest_revC/
/fpga/ramtest_revC_fast/
/fpga/ramtest_revC_fast/main.v
/fpga/ramtest_revC_fast/mem_tester/
/fpga/ramtest_revC_fast/mem_tester/mem_tester.v
/fpga/ramtest_revC_fast/quartus/
/fpga/ramtest_revC_fast/quartus/main.qpf
/fpga/ramtest_revC_fast/quartus/main.qsf
/fpga/ramtest_revC_fast/quartus/main.qws
/fpga/ramtest_revC_fast/quartus/main.rbf
/fpga/ramtest_revC_fast/quartus/main.sof
/fpga/ramtest_revC_fast/resetter/
/fpga/ramtest_revC_fast/resetter/resetter.v
/fpga/ramtest_revC_fast/rnd_vec_gen/
/fpga/ramtest_revC_fast/rnd_vec_gen/rnd_vec_gen.v
/fpga/ramtest_revC_fast/sim/
/fpga/ramtest_revC_fast/sim/c
/fpga/ramtest_revC_fast/sim/d
/fpga/ramtest_revC_fast/sim/l
/fpga/ramtest_revC_fast/sim/s
/fpga/ramtest_revC_fast/sim/tb.v
/fpga/ramtest_revC_fast/sim/vlog.opt
/fpga/ramtest_revC_fast/sim/wave.do
/fpga/ramtest_revC_fast/sram_control/
/fpga/ramtest_revC_fast/sram_control/sram_control.v
/fpga/ramtest_revC_slow/ ~~/fpga/ramtest_revC@57 (Prev)~~
/fpga/ramtest_revC_slow/quartus/10mhz.sof
/fpga/ramtest_revC_slow/quartus/12mhz.sof
/fpga/ramtest_revC_slow/quartus/20mhz.sof
/fpga/ramtest_revC_slow/quartus/24mhz.sof